erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

ARMv7/Exynos: Fix memory location assumptions

Browse source 
This patch cleans out a lot of unused variables in the
ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE
which is similar to CONFIG_RAMBASE on x86.
This gets rid of the hard coded assumption that on ARM
coreboot is always executed at the lowest DRAM address.
But in fact, this might not be true because we might want
coreboot to live at the end of RAM, or in SRAM

BUG=none
BRANCH=none
TEST=successfully booted on pit.

Change-Id: I03e992645f9eb730e39a521aa21f702959311f74
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168645
Reviewed-by: David Hendrix <dhendrix@chromium.org>
Tested-by: David Hendrix <dhendrix@chromium.org>
This commit is contained in:
Stefan Reinauer 2013-09-09 14:37:03 -07:00 • committed by chrome-internal-fetch
commit 15b87892eb
5 changed files with 26 additions and 67 deletions
Download patch file Download diff file Expand all files Collapse all files

19
src/cpu/samsung/exynos5250/Kconfig
View file

@ -38,6 +38,9 @@ config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x0A000
config SYS_SDRAM_BASE
hex
default 0x40000000
# Example SRAM/iRAM map for Exynos5250 platform:
#
@ -54,9 +57,9 @@ config ROMSTAGE_BASE
hex
default 0x02030000
config ROMSTAGE_SIZE
config RAMSTAGE_BASE
hex
default 0x10000
default SYS_SDRAM_BASE
# Stack may reside in either IRAM or DRAM. We will define it to live
# at the top of IRAM for now.
@ -90,18 +93,6 @@ config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x02058000
config TTB_SIZE
hex "size of the TTB buffer"
default 0x4000
config SYS_SDRAM_BASE
hex
default 0x40000000
config COREBOOT_TABLES_SIZE
hex
default 0x4000000
choice CONSOLE_SERIAL_UART_CHOICES
prompt "Serial Console UART"
default CONSOLE_SERIAL_UART3

24
src/cpu/samsung/exynos5420/Kconfig
View file

@ -40,6 +40,9 @@ config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x0A000
config SYS_SDRAM_BASE
hex
default 0x20000000
# Example SRAM/iRAM map for Exynos5420 platform:
#
@ -63,9 +66,9 @@ config ROMSTAGE_BASE
hex
default 0x02030000
config ROMSTAGE_SIZE
config RAMSTAGE_BASE
hex
default 0x20000
default SYS_SDRAM_BASE
# Stack may reside in either IRAM or DRAM. We will define it to live
# at the top of IRAM for now.
@ -90,11 +93,6 @@ config STACK_BOTTOM
hex
default 0x0206f000
# The romstage stack must be large enough to contain the lzma buffer
config ROMSTAGE_STACK_SIZE
hex
default 0x4000
# STACK_SIZE is for the ramstage core and thread stacks.
# It must be a power of 2, to make the cpu_info computation work,
# and cpu_info needs to work to make SMP startup and threads work.
@ -116,18 +114,6 @@ config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x02058000
config TTB_SIZE
hex "size of the TTB buffer"
default 0x4000
config SYS_SDRAM_BASE
hex
default 0x20000000
config COREBOOT_TABLES_SIZE
hex
default 0x4000000
choice CONSOLE_SERIAL_UART_CHOICES
prompt "Serial Console UART"
default CONSOLE_SERIAL_UART3