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cpu/intel: Enter romstage without BIST

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When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.

Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2019-08-16 14:02:25 +03:00
commit 157b189f6b
47 changed files with 63 additions and 182 deletions
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3
src/mainboard/intel/baskingridge/romstage.c
View file

@ -63,7 +63,7 @@ const struct rcba_config_instruction rcba_config[] = {
RCBA_END_CONFIG,
};
void mainboard_romstage_entry(unsigned long bist)
void mainboard_romstage_entry(void)
{
struct pei_data pei_data = {
.pei_version = PEI_VERSION,
@ -136,7 +136,6 @@ void mainboard_romstage_entry(unsigned long bist)
.pei_data = &pei_data,
.gpio_map = &mainboard_gpio_map,
.rcba_config = &rcba_config[0],
.bist = bist,
.copy_spd = NULL,
};

9
src/mainboard/intel/d945gclf/romstage.c
View file

@ -19,7 +19,6 @@
#include <cpu/x86/lapic.h>
#include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
@ -117,12 +116,11 @@ static void early_ich7_init(void)
RCBA32(0x2034) = reg32;
}
void mainboard_romstage_entry(unsigned long bist)
void mainboard_romstage_entry(void)
{
int s3resume = 0, boot_mode = 0;
if (bist == 0)
enable_lapic();
enable_lapic();
ich7_enable_lpc();
/* Enable SuperIO PM */
@ -132,9 +130,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* Set up the console */
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected.\n");
boot_mode = 1;

4
src/mainboard/intel/dg41wv/romstage.c
View file

@ -19,7 +19,6 @@
#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
#include <northbridge/intel/x4x/iomap.h>
#include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/common/gpio.h>
@ -75,7 +74,7 @@ static void ich7_enable_lpc(void)
pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
}
void mainboard_romstage_entry(unsigned long bist)
void mainboard_romstage_entry(void)
{
// ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@ -89,7 +88,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init();
report_bist_failure(bist);
enable_smbus();
x4x_early_init();

4
src/mainboard/intel/dg43gt/romstage.c
View file

@ -20,7 +20,6 @@
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
#include <northbridge/intel/x4x/x4x.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <superio/winbond/common/winbond.h>
@ -68,7 +67,7 @@ static void ich10_enable_lpc(void)
pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);
}
void mainboard_romstage_entry(unsigned long bist)
void mainboard_romstage_entry(void)
{
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
u8 boot_path = 0;
@ -81,7 +80,6 @@ void mainboard_romstage_entry(unsigned long bist)
console_init();
report_bist_failure(bist);
enable_smbus();
x4x_early_init();