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soc/intel/braswell: Increase dcache size

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Increase the DRAM cache size for Braswell to address the
compilation error

    Cache as RAM area too full

when moving the mrc_cache writeback to romstage.  We need to increase
this first before landing the CL moving mrc_cache writeback to
romstage.

BUG=b:150502246
BRANCH=None
TEST=Able to successfully compile braswell boards

Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2020-09-29 10:05:00 -07:00
commit 156bc6f47a
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/braswell/Kconfig
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@ -93,7 +93,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex
default 0x4000
default 0x8000
help
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE