From 152914272c1068097891dceb76ae21924656abad Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 20 Jul 2024 13:48:16 +0200 Subject: [PATCH] device/azalia: Drop spurious read-back of STATESTS The STATESTS register is a very simple read/write-1-clear status register. OS drivers have to read and clear it all the time with- out any quirk handling. So it seems unlikely that this sequence was ever necessary for any coreboot-supported chip. More likely, that sequence was copied from the dance around the reset bit when Poulsbo support was added in commit be61a173512e ("Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board which uses it."). TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3. Change-Id: I1fbea8ffb71a2fcb4ce5f42b3cb8f816ec336c5b Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/89653 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/device/azalia_device.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 9cda449302..d130c5b998 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -48,7 +48,6 @@ enum cb_err azalia_exit_reset(u8 *base) static u16 codec_detect(u8 *base) { - struct stopwatch sw; u16 reg16; if (azalia_exit_reset(base) != CB_SUCCESS) @@ -71,20 +70,6 @@ static u16 codec_detect(u8 *base) /* clear STATESTS bits (BAR + 0x0e)[14:0] */ setbits16(base + HDA_STATESTS_REG, 0x7fff); - /* Wait for readback of register to - * match what was just written to it - */ - stopwatch_init_msecs_expire(&sw, 50); - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg16 = read16(base + HDA_STATESTS_REG); - } while ((reg16 != 0) && !stopwatch_expired(&sw)); - - /* Timeout occurred */ - if (stopwatch_expired(&sw)) - goto no_codec; - if (azalia_enter_reset(base) != CB_SUCCESS) goto no_codec;