From 150647a2fb7e20bc767019ae0e1492d54e2de121 Mon Sep 17 00:00:00 2001 From: Varun Upadhyay Date: Mon, 6 Oct 2025 00:05:38 +0530 Subject: [PATCH] ec/google/chromeec: Fix ACPI _CRS method generation for LPC memory range Enable _CRS method when EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE is configured, even without EC sync IRQ support. Previously, the _CRS method was only generated if EC_ENABLE_SYNC_IRQ or EC_ENABLE_SYNC_IRQ_GPIO was defined, causing LPC generic memory range configuration to be skipped on boards that don't use EC sync IRQ which will results in no communication between kernel and EC. This change ensures LPC memory range resources are properly exposed in ACPI considering the hardware limitations where the EC sync IRQ GPIO is not available for boards using LPC_GENERIC_MEMORY_RANGE. BUG=437459757 TEST=Build and verify EC LPC memory range is configured in ACPI tables on boards with EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE enabled by dumping ssdt tables and also verify 'ectool version' cmd. ectool version RO version: ojal-0.0.0-2db24f9+ RW version: ojal-0.0.0-2db24f9+ Change-Id: If63dd631029d2756451fad71a5556bc0b23f507d Signed-off-by: Varun Upadhyay Reviewed-on: https://review.coreboot.org/c/coreboot/+/89420 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/acpi/cros_ec.asl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 9cf1f66fb2..f29ca14efc 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -23,7 +23,8 @@ Device (CREC) #define EC_SYNC_SHARE_TYPE Exclusive #endif -#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO) +#if defined(EC_ENABLE_SYNC_IRQ) || defined(EC_ENABLE_SYNC_IRQ_GPIO) || \ +CONFIG(EC_GOOGLE_CHROMEEC_LPC_GENERIC_MEMORY_RANGE) Method (_CRS, 0x0, NotSerialized) { Name (RBUF, ResourceTemplate()