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mb/hp: Move compaq_8200_elite_sff_pc into snb_ivb_desktops variants

Browse source 
Tested to still boot, SeaBIOS -> Void Linux

Change-Id: I03d57c7e76ccdfccd58b2a6deab4dee87b02503a
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79545
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Riku Viitanen 2023-12-14 00:55:21 +02:00 • committed by Felix Singer
commit 14c671d90a
20 changed files with 43 additions and 437 deletions
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40
src/mainboard/hp/compaq_8200_elite_sff/Kconfig
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@ -1,40 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_INT15
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_BD82X6X
select USE_NATIVE_RAMINIT
select MEMORY_MAPPED_TPM
select MAINBOARD_HAS_TPM1
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select SUPERIO_NUVOTON_NPCD378
select MAINBOARD_HAS_LIBGFXINIT
select INTEL_GMA_HAVE_VBT
select MAINBOARD_USES_IFD_GBE_REGION
config CBFS_SIZE
default 0x2F0000
config MAINBOARD_DIR
default "hp/compaq_8200_elite_sff"
config MAINBOARD_PART_NUMBER
default "HP Compaq 8200 Elite SFF PC"
config DRAM_RESET_GATE_GPIO
int
default 60
config USBDEBUG_HCD_INDEX
int
default 2
endif

4
src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name
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@ -1,4 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
bool "Compaq 8200 Elite SFF"

7
src/mainboard/hp/compaq_8200_elite_sff/Makefile.mk
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@ -1,7 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

3
src/mainboard/hp/compaq_8200_elite_sff/acpi/ec.asl
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@ -1,3 +0,0 @@
/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

15
src/mainboard/hp/compaq_8200_elite_sff/acpi/platform.asl
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@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Method(_WAK, 1, NotSerialized)
{
// Generated by SSDT
\_SB.PCI0.LPCB.SIO0.SIOW (Arg0)
Return(Package(){0,0})
}
Method(_PTS, 1, NotSerialized)
{
// Generated by SSDT
\_SB.PCI0.LPCB.SIO0.SIOS (Arg0)
}

27
src/mainboard/hp/compaq_8200_elite_sff/acpi/superio.asl
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@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <superio/nuvoton/npcd378/acpi/superio.asl>
Scope (\_GPE)
{
Method (_L0D, 0, NotSerialized)
{
Notify (\_SB.PCI0.EHC1, 0x02)
Notify (\_SB.PCI0.EHC2, 0x02)
//FIXME: Add GBE device
//Notify (\_SB.PCI0.GBE, 0x02)
}
Method (_L09, 0, NotSerialized)
{
Notify (\_SB.PCI0.RP01, 0x02)
Notify (\_SB.PCI0.RP02, 0x02)
Notify (\_SB.PCI0.RP03, 0x02)
Notify (\_SB.PCI0.RP04, 0x02)
Notify (\_SB.PCI0.RP05, 0x02)
Notify (\_SB.PCI0.RP06, 0x02)
Notify (\_SB.PCI0.RP07, 0x02)
Notify (\_SB.PCI0.RP08, 0x02)
Notify (\_SB.PCI0.PEGP, 0x02)
}
}

9
src/mainboard/hp/compaq_8200_elite_sff/cmos.default
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@ -1,9 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
boot_option=Fallback
debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
gfx_uma_size=32M
psu_fan_lvl=3

72
src/mainboard/hp/compaq_8200_elite_sff/cmos.layout
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@ -1,72 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
400 3 h 0 psu_fan_lvl
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
421 1 e 9 sata_mode
# coreboot config options: northbridge
432 3 e 11 gfx_uma_size
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
9 0 AHCI
9 1 IDE
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
# -----------------------------------------------------------------
checksums
checksum 392 415 984

174
src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb
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@ -1,174 +0,0 @@
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
register "gfx.use_spread_spectrum_clock" = "0"
register "gpu_dp_b_hotplug" = "0"
register "gpu_dp_c_hotplug" = "0"
register "gpu_dp_d_hotplug" = "0"
# BTX mainboard: Reversed mapping
register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
device domain 0 on
subsystemid 0x103c 0x1495 inherit
device ref host_bridge on end # Host bridge Host bridge
device ref peg10 on end # PCIe Bridge for discrete graphics
device ref igd on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "0"
register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0801"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "true"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0xf"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x0"
register "usb_port_config" = "{
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 }
}"
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
device ref me_kt on end # Management Engine KT
device ref gbe on end # Intel Gigabit Ethernet
device ref ehci2 on end # USB2 EHCI #2
device ref hda on end # High Definition Audio controller
device ref pcie_rp1 on end # PCIe Port #1
device ref pcie_rp2 off end # PCIe Port #2
device ref pcie_rp3 off end # PCIe Port #3
device ref pcie_rp4 off end # PCIe Port #4
device ref pcie_rp5 on end # PCIe Port #5
device ref pcie_rp6 off end # PCIe Port #6
device ref pcie_rp7 on end # PCIe Port #7
device ref pcie_rp8 on end # PCIe Port #8
device ref ehci1 on end # USB2 EHCI #1
device ref pci_bridge on end # PCI bridge
device ref lpc on # LPC bridge PCI-LPC bridge
chip superio/common
device pnp 2e.ff on # passes SIO base addr to SSDT gen
chip superio/nuvoton/npcd378
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Parallel port
# global
# serialice: Vendor writes:
irq 0x14 = 0x9c
irq 0x1c = 0xa8
irq 0x1d = 0x08
irq 0x22 = 0x3f
irq 0x1a = 0xb0
# dumped from superiotool:
irq 0x1b = 0x1e
irq 0x27 = 0x08
irq 0x2a = 0x20
irq 0x2d = 0x01
# parallel port
io 0x60 = 0x378
irq 0x70 = 0x07
drq 0x74 = 0x01
end
device pnp 2e.2 off # COM1
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # COM2, IR
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 on # LED control
io 0x60 = 0x600
# IOBASE[0h] = bit0 LED red / green
# IOBASE[0h] = bit1-4 LED PWM duty cycle
# IOBASE[1h] = bit6 SWCC
io 0x62 = 0x610
# IOBASE [0h] = GPES
# IOBASE [1h] = GPEE
# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
# IOBASE [8h:bh] = GPS
# IOBASE [ch:fh] = GPE
end
device pnp 2e.5 on # Mouse
irq 0x70 = 0xc
end
device pnp 2e.6 on # Keyboard
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 0x01
# serialice: Vendor writes:
drq 0xf0 = 0x40
end
device pnp 2e.7 on # WDT ?
io 0x60 = 0x620
end
device pnp 2e.8 on # HWM
io 0x60 = 0x800
# IOBASE[0h:feh] HWM page
# IOBASE[ffh] bit0-bit3 page selector
drq 0xf0 = 0x20
drq 0xf1 = 0x01
drq 0xf2 = 0x40
drq 0xf3 = 0x01
drq 0xf4 = 0x66
drq 0xf5 = 0x67
drq 0xf6 = 0x66
drq 0xf7 = 0x01
end
device pnp 2e.f on # GPIO OD ?
drq 0xf1 = 0x97
drq 0xf2 = 0x01
drq 0xf5 = 0x08
drq 0xfe = 0x80
end
device pnp 2e.15 on # BUS ?
io 0x60 = 0x0680
io 0x62 = 0x0690
end
device pnp 2e.1c on # Suspend Control ?
io 0x60 = 0x640
# writing to IOBASE[5h]
# 0x0: Power off
# 0x9: Power off and bricked until CMOS battery removed
end
device pnp 2e.1e on # GPIO ?
io 0x60 = 0x660
drq 0xf4 = 0x01
# skip the following, as it
# looks like remapped registers
#drq 0xf5 = 0x06
#drq 0xf6 = 0x60
#drq 0xfe = 0x03
end
end
end
end
chip drivers/pc80/tpm
device pnp 4e.0 on end # TPM module
end
end
device ref sata1 on end # SATA Controller 1
device ref smbus on end # SMBus
device ref sata2 off end # SATA Controller 2
device ref thermal off end # Thermal
end
end
end

28
src/mainboard/hp/compaq_8200_elite_sff/dsdt.asl
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@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018 // OEM revision
)
{
#include <acpi/dsdt_top.asl>
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
}

40
src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
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@ -1,40 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
#if CONFIG(GENERATE_SMBIOS_TABLES)
static int mainboard_smbios_data(struct device *dev, int *handle,
unsigned long *current)
{
int len = 0;
// add IPMI Device Information
len += smbios_write_type38(
current, handle,
SMBIOS_BMC_INTERFACE_KCS,
0x20, // IPMI Version
0x20, // I2C address
0xff, // no NV storage
0, // IO port interface address
0,
0); // no IRQ
return len;
}
#endif
static void mainboard_enable(struct device *dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
#if CONFIG(GENERATE_SMBIOS_TABLES)
dev->ops->get_smbios_data = mainboard_smbios_data;
#endif
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

10
src/mainboard/hp/snb_ivb_desktops/Kconfig
View file

@ -17,6 +17,11 @@ config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
select SUPERIO_NUVOTON_NPCD378
select USE_NATIVE_RAMINIT
config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
select SOUTHBRIDGE_INTEL_BD82X6X
select BOARD_ROMSIZE_KB_8192
config BOARD_HP_COMPAQ_ELITE_8300_USDT
select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
select SOUTHBRIDGE_INTEL_C216
@ -45,17 +50,20 @@ config VBOOT
select VBOOT_VBNV_FLASH
config CBFS_SIZE
default 0x570000
default 0x2F0000 if BOARD_ROMSIZE_KB_8192
default 0x570000 if BOARD_ROMSIZE_KB_16384
config MAINBOARD_DIR
default "hp/snb_ivb_desktops"
config VARIANT_DIR
default "compaq_8200_elite_sff" if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
default "compaq_elite_8300_usdt" if BOARD_HP_COMPAQ_ELITE_8300_USDT
default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION
default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION
config MAINBOARD_PART_NUMBER
default "HP Compaq 8200 Elite SFF PC" if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
default "HP Compaq Elite 8300 USDT" if BOARD_HP_COMPAQ_ELITE_8300_USDT
default "HP Z220 CMT Workstation" if BOARD_HP_Z220_CMT_WORKSTATION
default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION

3
src/mainboard/hp/snb_ivb_desktops/Kconfig.name
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@ -1,5 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
bool "Compaq 8200 Elite SFF"
config BOARD_HP_COMPAQ_ELITE_8300_USDT
bool "Compaq Elite 8300 USDT"

0
src/mainboard/hp/compaq_8200_elite_sff/board_info.txt → src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/board_info.txt
View file

0
src/mainboard/hp/compaq_8200_elite_sff/data.vbt → src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/data.vbt
View file

17
src/mainboard/hp/compaq_8200_elite_sff/early_init.c → src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/early_init.c
View file

@ -7,23 +7,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
};
void bootblock_mainboard_early_init(void)
{
if (CONFIG(CONSOLE_SERIAL))

0
src/mainboard/hp/compaq_8200_elite_sff/gma-mainboard.ads → src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/gma-mainboard.ads
View file

0
src/mainboard/hp/compaq_8200_elite_sff/gpio.c → src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/gpio.c
View file

0
src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c → src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/hda_verb.c
View file

31
src/mainboard/hp/snb_ivb_desktops/variants/compaq_8200_elite_sff/overridetree.cb Normal file
View file

@ -0,0 +1,31 @@
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x103c 0x1495 inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "sata_port_map" = "0xf"
register "spi_uvscc" = "0x0"
register "usb_port_config" = "{
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
{ 1, 0, -1 },
}"
device ref pcie_rp7 on end # PCIe Port #7
device ref pcie_rp8 on end # PCIe Port #8
end
end
end