From 13a5e0e205d2435b9716500f06c6d2b16472a6e4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sat, 19 Nov 2016 16:39:21 +0200
Subject: [PATCH] UPSTREAM: intel car: Move pre-ram stack guard lower

SPD data alone consumes 0x400 of pre-ram stack, so the guard was
initially set too high, printing spurious "smashed stack detected"
messages at end of romstage.

Use the same stack size as haswell.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17501
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I24fff6228bc5207750a3c4bf8cf34e91cf35e716
Reviewed-on: https://chromium-review.googlesource.com/413245
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/cpu/intel/car/romstage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index d04b6e120c..4f600342ec 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -16,7 +16,7 @@
 #include <cpu/intel/romstage.h>
 #include <program_loading.h>
 
-#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x800
+#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
 
 void * asmlinkage romstage_main(unsigned long bist)
 {