diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index ddb54a56c0..e9001f09b2 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -32,12 +32,10 @@ static int tegra_i2c_send_recv(struct tegra_i2c_regs *regs, int read, { while (data_len) { uint32_t status = read32(®s->fifo_status); - int tx_empty = - status & TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK; - tx_empty >>= TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT; - int rx_full = - status & TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK; - rx_full >>= TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; + int tx_empty = status & I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK; + tx_empty >>= I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT; + int rx_full = status & I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK; + rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; while (header_words && tx_empty) { write32(*headers++, ®s->tx_packet_fifo); @@ -73,19 +71,17 @@ static int tegra_i2c_send_recv(struct tegra_i2c_regs *regs, int read, uint32_t transfer_status = read32(®s->packet_transfer_status); - if (transfer_status & TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK) { + if (transfer_status & I2C_PKT_STATUS_NOACK_ADDR) { printk(BIOS_ERR, "%s: The address was not acknowledged.\n", __func__); return -1; - } else if (transfer_status & - TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK) { + } else if (transfer_status & I2C_PKT_STATUS_NOACK_DATA) { printk(BIOS_ERR, "%s: The data was not acknowledged.\n", __func__); return -1; - } else if (transfer_status & - TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK) { + } else if (transfer_status & I2C_PKT_STATUS_ARB_LOST) { printk(BIOS_ERR, "%s: Lost arbitration.\n", __func__); @@ -108,25 +104,22 @@ static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart, return -1; } - headers[0] = (0 << IOHEADER_WORD0_PROTHDRSZ_SHIFT) | - (1 << IOHEADER_WORD0_PKTID_SHIFT) | - (bus << IOHEADER_WORD0_CONTROLLER_ID_SHIFT) | - IOHEADER_WORD0_PROTOCOL_I2C | - IOHEADER_WORD0_PKTTYPE_REQUEST; + headers[0] = (0 << IOHEADER_PROTHDRSZ_SHIFT) | + (1 << IOHEADER_PKTID_SHIFT) | + (bus << IOHEADER_CONTROLLER_ID_SHIFT) | + IOHEADER_PROTOCOL_I2C | IOHEADER_PKTTYPE_REQUEST; - headers[1] = (data_len - 1) << IOHEADER_WORD1_PAYLOADSIZE_SHIFT; + headers[1] = (data_len - 1) << IOHEADER_PAYLOADSIZE_SHIFT; uint32_t slave_addr = (chip << 1) | (read ? 1 : 0); - headers[2] = IOHEADER_I2C_REQ_ADDRESS_MODE_7BIT | + headers[2] = IOHEADER_I2C_REQ_ADDR_MODE_7BIT | (slave_addr << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT); if (read) - headers[2] |= IOHEADER_I2C_REQ_READ_WRITE_READ; - else - headers[2] |= IOHEADER_I2C_REQ_READ_WRITE_WRITE; + headers[2] |= IOHEADER_I2C_REQ_READ; if (restart) - headers[2] |= IOHEADER_I2C_REQ_REPEAT_START_STOP_START; + headers[2] |= IOHEADER_I2C_REQ_REPEAT_START; if (cont) - headers[2] |= IOHEADER_I2C_REQ_CONTINUE_XFER_MASK; + headers[2] |= IOHEADER_I2C_REQ_CONTINUE_XFER; return tegra_i2c_send_recv(regs, read, headers, ARRAY_SIZE(headers), data, data_len); @@ -136,8 +129,7 @@ static int i2c_readwrite(unsigned bus, unsigned chip, unsigned addr, unsigned alen, uint8_t *buf, unsigned len, int read) { const uint32_t max_payload = - (IOHEADER_WORD1_PAYLOADSIZE_MASK + 1) >> - IOHEADER_WORD1_PAYLOADSIZE_SHIFT; + (IOHEADER_PAYLOADSIZE_MASK + 1) >> IOHEADER_PAYLOADSIZE_SHIFT; uint8_t abuf[sizeof(addr)]; int i; @@ -176,5 +168,5 @@ void i2c_init(unsigned bus) { struct tegra_i2c_regs * const regs = tegra_i2c_bases[bus]; - write32(TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK, ®s->cnfg); + write32(I2C_CNFG_PACKET_MODE_EN, ®s->cnfg); } diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index 630d890c38..997ec9c18f 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -24,133 +24,90 @@ void i2c_init(unsigned bus); -#define IOHEADER_BITFIELD(name, shift, mask) \ - IOHEADER_##name##_SHIFT = shift, \ - IOHEADER_##name##_MASK = \ - mask << IOHEADER_##name##_SHIFT - -#define IOHEADER_BITFIELD_VAL(field, name, val) \ - IOHEADER_##field##_##name = \ - val << IOHEADER_##field##_SHIFT - enum { /* Word 0 */ - IOHEADER_BITFIELD(WORD0_PROTHDRSZ, 28, 0x3), - - IOHEADER_BITFIELD(WORD0_PKTID, 16, 0xff), - - IOHEADER_BITFIELD(WORD0_CONTROLLER_ID, 12, 0xf), - - IOHEADER_BITFIELD(WORD0_PROTOCOL, 4, 0xf), - IOHEADER_BITFIELD_VAL(WORD0_PROTOCOL, I2C, 1), - - IOHEADER_BITFIELD(WORD0_PKTTYPE, 0, 0x7), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, REQUEST, 0), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, RESPONSE, 1), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, INTERRUPT, 2), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, STOP, 3), + IOHEADER_PROTHDRSZ_SHIFT = 28, + IOHEADER_PROTHDRSZ_MASK = 0x3 << IOHEADER_PROTHDRSZ_SHIFT, + IOHEADER_PKTID_SHIFT = 16, + IOHEADER_PKTID_MASK = 0xff << IOHEADER_PKTID_SHIFT, + IOHEADER_CONTROLLER_ID_SHIFT = 12, + IOHEADER_CONTROLLER_ID_MASK = 0xf << IOHEADER_CONTROLLER_ID_SHIFT, + IOHEADER_PROTOCOL_SHIFT = 4, + IOHEADER_PROTOCOL_MASK = 0xf << IOHEADER_PROTOCOL_SHIFT, + IOHEADER_PROTOCOL_I2C = 1 << IOHEADER_PROTOCOL_SHIFT, + IOHEADER_PKTTYPE_SHIFT = 0, + IOHEADER_PKTTYPE_MASK = 0x7 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_REQUEST = 0 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_RESPONSE = 1 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_INTERRUPT = 2 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_STOP = 3 << IOHEADER_PKTTYPE_SHIFT, /* Word 1 */ - IOHEADER_BITFIELD(WORD1_PAYLOADSIZE, 0, 0xfff) + IOHEADER_PAYLOADSIZE_SHIFT = 0, + IOHEADER_PAYLOADSIZE_MASK = 0xfff << IOHEADER_PAYLOADSIZE_SHIFT }; enum { - IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_FREQ_SHIFT, 25, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, END, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, EACH, 1), - - IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_ENABLE, 24, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_HS_MODE, 22, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_CONTINUE_ON_NACK, 21, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_SEND_START_BYTE, 20, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_READ_WRITE, 19, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, WRITE, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, READ, 1), - - IOHEADER_BITFIELD(I2C_REQ_ADDRESS_MODE, 18, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 7BIT, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 10BIT, 1), - - IOHEADER_BITFIELD(I2C_REQ_IE, 17, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_REPEAT_START_STOP, 16, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, STOP, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, START, 1), - - IOHEADER_BITFIELD(I2C_REQ_CONTINUE_XFER, 15, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_HS_MASTER_ADDR, 12, 0x7), - - IOHEADER_BITFIELD(I2C_REQ_SLAVE_ADDR, 0, 0x3ff) + IOHEADER_I2C_REQ_RESP_FREQ_MASK = 0x1 << 25, + IOHEADER_I2C_REQ_RESP_FREQ_END = 0 << 25, + IOHEADER_I2C_REQ_RESP_FREQ_EACH = 1 << 25, + IOHEADER_I2C_REQ_RESP_ENABLE = 0x1 << 24, + IOHEADER_I2C_REQ_HS_MODE = 0x1 << 22, + IOHEADER_I2C_REQ_CONTINUE_ON_NACK = 0x1 << 21, + IOHEADER_I2C_REQ_SEND_START_BYTE = 0x1 << 20, + IOHEADER_I2C_REQ_READ = 0x1 << 19, + IOHEADER_I2C_REQ_ADDR_MODE_MASK = 0x1 << 18, + IOHEADER_I2C_REQ_ADDR_MODE_7BIT = 0 << 18, + IOHEADER_I2C_REQ_ADDR_MODE_10BIT = 1 << 18, + IOHEADER_I2C_REQ_IE = 0x1 << 17, + IOHEADER_I2C_REQ_REPEAT_START = 0x1 << 16, + IOHEADER_I2C_REQ_STOP = 0x0 << 16, + IOHEADER_I2C_REQ_CONTINUE_XFER = 0x1 << 15, + IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT = 12, + IOHEADER_I2C_REQ_HS_MASTER_ADDR_MASK = + 0x7 << IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT, + IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT = 0, + IOHEADER_I2C_REQ_SLAVE_ADDR_MASK = + 0x3ff << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT }; enum { - TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT = 15, - TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_MASK = - 0x1 << TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT, - TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12, - TEGRA_I2C_CNFG_DEBOUNCE_CNT_MASK = - 0x7 << TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT, - TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT = 11, - TEGRA_I2C_CNFG_NEW_MASTER_FSM_MASK = - 0x1 << TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT, - TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT = 10, - TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK = - 0x1 << TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT, - TEGRA_I2C_CNFG_SEND_SHIFT = 9, - TEGRA_I2C_CNFG_SEND_MASK = 0x1 << TEGRA_I2C_CNFG_SEND_SHIFT, - TEGRA_I2C_CNFG_NOACK_SHIFT = 8, - TEGRA_I2C_CNFG_NOACK_MASK = 0x1 << TEGRA_I2C_CNFG_NOACK_SHIFT, - TEGRA_I2C_CNFG_CMD2_SHIFT = 7, - TEGRA_I2C_CNFG_CMD2_MASK = 0x1 << TEGRA_I2C_CNFG_CMD2_SHIFT, - TEGRA_I2C_CNFG_CMD1_SHIFT = 6, - TEGRA_I2C_CNFG_CMD1_MASK = 0x1 << TEGRA_I2C_CNFG_CMD1_SHIFT, - TEGRA_I2C_CNFG_START_SHIFT = 5, - TEGRA_I2C_CNFG_START_MASK = 0x1 << TEGRA_I2C_CNFG_START_SHIFT, - TEGRA_I2C_CNFG_SLV2_SHIFT = 4, - TEGRA_I2C_CNFG_SLV2_MASK = 0x1 << TEGRA_I2C_CNFG_SLV2_SHIFT, - TEGRA_I2C_CNFG_LENGTH_SHIFT = 1, - TEGRA_I2C_CNFG_LENGTH_MASK = 0x7 << TEGRA_I2C_CNFG_LENGTH_SHIFT, - TEGRA_I2C_CNFG_A_MOD_SHIFT = 0, - TEGRA_I2C_CNFG_A_MOD_MASK = 0x1 << TEGRA_I2C_CNFG_A_MOD_SHIFT + I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT = 0x1 << 15, + I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12, + I2C_CNFG_DEBOUNCE_CNT_MASK = 0x7 << I2C_CNFG_DEBOUNCE_CNT_SHIFT, + I2C_CNFG_NEW_MASTER_FSM = 0x1 << 11, + I2C_CNFG_PACKET_MODE_EN = 0x1 << 10, + I2C_CNFG_SEND = 0x1 << 9, + I2C_CNFG_NOACK = 0x1 << 8, + I2C_CNFG_CMD2 = 0x1 << 7, + I2C_CNFG_CMD1 = 0x1 << 6, + I2C_CNFG_START = 0x1 << 5, + I2C_CNFG_SLV2_SHIFT = 4, + I2C_CNFG_SLV2_MASK = 0x1 << I2C_CNFG_SLV2_SHIFT, + I2C_CNFG_LENGTH_SHIFT = 1, + I2C_CNFG_LENGTH_MASK = 0x7 << I2C_CNFG_LENGTH_SHIFT, + I2C_CNFG_A_MOD = 0x1 << 0, }; enum { - TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT = 24, - TEGRA_I2C_PKT_STATUS_COMPLETE_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT, - TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT = 16, - TEGRA_I2C_PKT_STATUS_PKT_ID_MASK = - 0xff << TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT, - TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT = 4, - TEGRA_I2C_PKT_STATUS_BYTENUM_MASK = - 0xfff << TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT, - TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT = 3, - TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT, - TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT = 2, - TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT, - TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT = 1, - TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT, - TEGRA_I2C_PKT_STATUS_BUSY_SHIFT = 0, - TEGRA_I2C_PKT_STATUS_BUSY_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_BUSY_SHIFT, + I2C_PKT_STATUS_COMPLETE = 0x1 << 24, + I2C_PKT_STATUS_PKT_ID_SHIFT = 16, + I2C_PKT_STATUS_PKT_ID_MASK = 0xff << I2C_PKT_STATUS_PKT_ID_SHIFT, + I2C_PKT_STATUS_BYTENUM_SHIFT = 4, + I2C_PKT_STATUS_BYTENUM_MASK = 0xfff << I2C_PKT_STATUS_BYTENUM_SHIFT, + I2C_PKT_STATUS_NOACK_ADDR = 0x1 << 3, + I2C_PKT_STATUS_NOACK_DATA = 0x1 << 2, + I2C_PKT_STATUS_ARB_LOST = 0x1 << 1, + I2C_PKT_STATUS_BUSY = 0x1 << 0 }; enum { - TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4, - TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK = - 0xf << TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT, - - TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0, - TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK = - 0xf << TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT + I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4, + I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK = + 0xf << I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT, + I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0, + I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK = + 0xf << I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT }; extern void * const tegra_i2c_bases[];