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Refactor copy_and_run so that it uses a single code base instead of

Browse source 
3 (with one of them way too much assembler code).

On the way, I had to make some changes to the way the code is built, 
which is an effort I want to expand over time.
Right now, large portions of the in-ROM part of coreboot is compiled as 
a single file, with lots of .c files including other .c files.
That has its justification for pre-raminit code, but it also affects 
lots of post-raminit code (memcpy doesn't really make sense before 
raminit, or at least CAR)

The coreboot_apc code (AMD boards) gained some .c includes because I 
don't know that part of the code enough to really rework it and only 
have limited possibilities to test it. The includes should give an 
identical situation for this part of the code.

This change was posted as set of 6 patches to the list, but they
were mostly split for review purposes, hence commit them all at once.
They can still be backed up using the patch files, if necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2009-04-30 07:07:22 +00:00
commit 12aba82e55
64 changed files with 129 additions and 473 deletions
Download patch file Download diff file Expand all files Collapse all files

5
src/mainboard/amd/dbm690t/cache_as_ram_auto.c
View file

@ -37,6 +37,7 @@
#define SMBUS_HUB 0x71
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -54,10 +55,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/amd/pistachio/cache_as_ram_auto.c
View file

@ -31,6 +31,7 @@
#define DIMM1 0x51
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -48,10 +49,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

3
src/mainboard/amd/serengeti_cheetah/apc_auto.c
View file

@ -21,12 +21,15 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "./arch/i386/lib/printk_init.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "arch/i386/lib/console.c"
#include "lib/uart8250.c"
#include "console/vtxprintf.c"
#if 0
static void post_code(uint8_t value) {

4
src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
View file

@ -24,6 +24,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -63,9 +64,6 @@ static void post_code(uint8_t value) {
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"

2
src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
View file

@ -136,7 +136,7 @@ default ROM_SIZE=524288
#FALLBACK: 512K - 4K
default FALLBACK_SIZE=0x7f000
#FAILOVER: 4k
default FAILOVER_SIZE=0x01000
default FAILOVER_SIZE=0x02000
#more 1M for pgtbl
#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.

5
src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
View file

@ -45,6 +45,7 @@
#define FAM10_SET_FIDVID_CORE_RANGE 0
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -81,10 +82,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
#if (USE_FAILOVER_IMAGE == 0)
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdfam10/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

4
src/mainboard/arima/hdama/cache_as_ram_auto.c
View file

@ -21,10 +21,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/asus/a8n_e/cache_as_ram_auto.c
View file

@ -38,6 +38,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -54,10 +55,6 @@
/* Used by ck894_early_setup(). */
#define CK804_NUM 1
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"

4
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
View file

@ -43,6 +43,7 @@ unsigned int get_sbdn(unsigned bus);
/* #define DEBUG_SMBUS 1 */
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -56,9 +57,6 @@ unsigned int get_sbdn(unsigned bus);
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

4
src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
View file

@ -47,6 +47,7 @@ unsigned int get_sbdn(unsigned bus);
/* #define DEBUG_SMBUS 1 */
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -61,9 +62,6 @@ unsigned int get_sbdn(unsigned bus);
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/broadcom/blast/cache_as_ram_auto.c
View file

@ -11,6 +11,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -40,10 +41,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
View file

@ -48,6 +48,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -85,10 +86,6 @@
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

5
src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
View file

@ -46,6 +46,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -82,10 +83,6 @@
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

5
src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
View file

@ -51,6 +51,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -87,10 +88,6 @@
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

5
src/mainboard/ibm/e325/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/ibm/e326/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

10
src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
View file

@ -24,6 +24,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -52,15 +53,6 @@
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
// TODO: This doesn't compile at the moment. Fix later.
// #if CONFIG_USE_PRINTK_IN_CAR == 1
// #include "lib/uart8250.c"
// #include "console/vtxprintf.c"
// #include "arch/i386/lib/printk_init.c"
// #endif
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"

10
src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
View file

@ -24,6 +24,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -52,15 +53,6 @@
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
// TODO: This doesn't compile at the moment. Fix later.
// #if CONFIG_USE_PRINTK_IN_CAR == 1
// #include "lib/uart8250.c"
// #include "console/vtxprintf.c"
// #include "arch/i386/lib/printk_init.c"
// #endif
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"

10
src/mainboard/iwill/dk8x/cache_as_ram_auto.c
View file

@ -24,6 +24,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -52,15 +53,6 @@
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
// TODO: This doesn't compile at the moment. Fix later.
// #if CONFIG_USE_PRINTK_IN_CAR == 1
// #include "lib/uart8250.c"
// #include "console/vtxprintf.c"
// #include "arch/i386/lib/printk_init.c"
// #endif
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"

5
src/mainboard/kontron/986lcd-m/auto.c
View file

@ -23,6 +23,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
@ -45,10 +46,6 @@
#include "northbridge/intel/i945/udelay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
#include "northbridge/intel/i945/ich7.h"

5
src/mainboard/msi/ms7135/cache_as_ram_auto.c
View file

@ -38,6 +38,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -56,10 +57,6 @@
#define CK804_USE_NIC 1
#define CK804_USE_ACI 1
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"

4
src/mainboard/msi/ms7260/cache_as_ram_auto.c
View file

@ -50,6 +50,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -84,9 +85,6 @@
#if USE_FAILOVER_IMAGE == 0
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"

5
src/mainboard/msi/ms9185/cache_as_ram_auto.c
View file

@ -47,6 +47,7 @@
#define DEBUG_SMBUS 1
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -75,10 +76,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"

5
src/mainboard/msi/ms9282/cache_as_ram_auto.c
View file

@ -41,6 +41,7 @@
#define DEBUG_SMBUS 1
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -57,10 +58,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/newisys/khepri/cache_as_ram_auto.c
View file

@ -7,6 +7,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -37,10 +38,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
View file

@ -46,6 +46,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -82,10 +83,6 @@
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

5
src/mainboard/sunw/ultra40/cache_as_ram_auto.c
View file

@ -14,6 +14,7 @@
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -32,10 +33,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

3
src/mainboard/supermicro/h8dme/apc_auto.c
View file

@ -48,6 +48,9 @@
#endif
#include "arch/i386/lib/console.c"
#include "lib/uart8250.c"
#include "console/vtxprintf.c"
#include "./arch/i386/lib/printk_init.c"
#if 0
static void post_code(uint8_t value) {

5
src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
View file

@ -40,6 +40,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -75,10 +76,6 @@
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

3
src/mainboard/supermicro/h8dmr/apc_auto.c
View file

@ -48,6 +48,9 @@
#endif
#include "arch/i386/lib/console.c"
#include "lib/uart8250.c"
#include "console/vtxprintf.c"
#include "./arch/i386/lib/printk_init.c"
#if 0
static void post_code(uint8_t value) {

5
src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
View file

@ -44,6 +44,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -79,10 +80,6 @@
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

5
src/mainboard/technexion/tim8690/cache_as_ram_auto.c
View file

@ -37,6 +37,7 @@
#define SMBUS_HUB 0x71
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -54,10 +55,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

10
src/mainboard/tyan/s2735/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -27,10 +28,6 @@ static void post_code(uint8_t value) {
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/e7501/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@ -259,6 +256,11 @@ cpu_reset_x:
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
#ifdef CONFIG_DEACTIVATE_CAR
print_debug("Deactivating CAR");
#include CONFIG_DEACTIVATE_CAR_FILE
print_debug(" - Done.\r\n");
#endif
/*copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
/* We will not return */

5
src/mainboard/tyan/s2850/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -32,10 +33,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/tyan/s2875/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/tyan/s2880/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -22,10 +23,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/tyan/s2881/cache_as_ram_auto.c
View file

@ -8,6 +8,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -38,10 +39,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/tyan/s2882/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/tyan/s2885/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -32,10 +33,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

4
src/mainboard/tyan/s2891/cache_as_ram_auto.c
View file

@ -9,6 +9,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -27,9 +28,6 @@
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/tyan/s2892/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/tyan/s2895/cache_as_ram_auto.c
View file

@ -12,6 +12,7 @@
#endif
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -47,10 +48,6 @@
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

5
src/mainboard/tyan/s2912/cache_as_ram_auto.c
View file

@ -46,6 +46,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -82,10 +83,6 @@
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

5
src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
View file

@ -39,6 +39,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@ -78,10 +79,6 @@ static void post_code(u8 value) {
#include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"

5
src/mainboard/tyan/s4880/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

5
src/mainboard/tyan/s4882/cache_as_ram_auto.c
View file

@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@ -20,10 +21,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"

6
src/mainboard/via/vt8454c/auto.c
View file

@ -119,6 +119,12 @@ static void main(unsigned long bist)
sdram_set_registers(cx700);
enable_shadow_ram(cx700);
sdram_enable(cx700);
#ifdef CONFIG_DEACTIVATE_CAR
print_debug("Deactivating CAR");
#include CONFIG_DEACTIVATE_CAR_FILE
print_debug(" - Done.\r\n");
#endif
copy_and_run(0);
}