From 12368bf5d8e11a562b0639b5dbf879ac8f870876 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Philipp=20Gro=C3=9F?= Date: Tue, 24 Dec 2024 15:34:19 +0100 Subject: [PATCH] mb/asrock: Add Z87 Pro4 (Haswell) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - HDMI-Out Port - DVI-D Port - D-Sub Port - RJ-45 Gigabit LAN Port - All four USB 2.0 Ports - All four USB 3.1 Gen1 Ports - Vertical Type A USB 3.1 Gen1 (located next to RAM slots) - All six SATA3 6.0 Gb/s connectors - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not working: - Both USB 3.1 Gen1 headers (also not working on vendor firmware, possible hardware defect) not (yet) tested: - IR header - COM Port header - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Signed-off-by: Jan Philipp Groß Reviewed-on: https://review.coreboot.org/c/coreboot/+/85756 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/asrock/z87_pro4/Kconfig | 27 +++ src/mainboard/asrock/z87_pro4/Kconfig.name | 4 + src/mainboard/asrock/z87_pro4/Makefile.mk | 6 + src/mainboard/asrock/z87_pro4/acpi/ec.asl | 3 + .../asrock/z87_pro4/acpi/platform.asl | 10 + .../asrock/z87_pro4/acpi/superio.asl | 3 + src/mainboard/asrock/z87_pro4/board_info.txt | 7 + src/mainboard/asrock/z87_pro4/bootblock.c | 32 +++ src/mainboard/asrock/z87_pro4/data.vbt | Bin 0 -> 6144 bytes src/mainboard/asrock/z87_pro4/devicetree.cb | 135 +++++++++++++ src/mainboard/asrock/z87_pro4/dsdt.asl | 27 +++ .../asrock/z87_pro4/gma-mainboard.ads | 17 ++ src/mainboard/asrock/z87_pro4/gpio.c | 184 ++++++++++++++++++ src/mainboard/asrock/z87_pro4/hda_verb.c | 28 +++ src/mainboard/asrock/z87_pro4/romstage.c | 36 ++++ 15 files changed, 519 insertions(+) create mode 100644 src/mainboard/asrock/z87_pro4/Kconfig create mode 100644 src/mainboard/asrock/z87_pro4/Kconfig.name create mode 100644 src/mainboard/asrock/z87_pro4/Makefile.mk create mode 100644 src/mainboard/asrock/z87_pro4/acpi/ec.asl create mode 100644 src/mainboard/asrock/z87_pro4/acpi/platform.asl create mode 100644 src/mainboard/asrock/z87_pro4/acpi/superio.asl create mode 100644 src/mainboard/asrock/z87_pro4/board_info.txt create mode 100644 src/mainboard/asrock/z87_pro4/bootblock.c create mode 100644 src/mainboard/asrock/z87_pro4/data.vbt create mode 100644 src/mainboard/asrock/z87_pro4/devicetree.cb create mode 100644 src/mainboard/asrock/z87_pro4/dsdt.asl create mode 100644 src/mainboard/asrock/z87_pro4/gma-mainboard.ads create mode 100644 src/mainboard/asrock/z87_pro4/gpio.c create mode 100644 src/mainboard/asrock/z87_pro4/hda_verb.c create mode 100644 src/mainboard/asrock/z87_pro4/romstage.c diff --git a/src/mainboard/asrock/z87_pro4/Kconfig b/src/mainboard/asrock/z87_pro4/Kconfig new file mode 100644 index 0000000000..dee318d726 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87_PRO4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87_pro4" + +config MAINBOARD_PART_NUMBER + default "Z87 Pro4" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: LAN_USB23 (Upper) + # Header: USB_4_5 +endif diff --git a/src/mainboard/asrock/z87_pro4/Kconfig.name b/src/mainboard/asrock/z87_pro4/Kconfig.name new file mode 100644 index 0000000000..61eed18b6d --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87_PRO4 + bool "Z87 Pro4" diff --git a/src/mainboard/asrock/z87_pro4/Makefile.mk b/src/mainboard/asrock/z87_pro4/Makefile.mk new file mode 100644 index 0000000000..c3cf55d397 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87_pro4/acpi/ec.asl b/src/mainboard/asrock/z87_pro4/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_pro4/acpi/platform.asl b/src/mainboard/asrock/z87_pro4/acpi/platform.asl new file mode 100644 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87_pro4/acpi/superio.asl b/src/mainboard/asrock/z87_pro4/acpi/superio.asl new file mode 100644 index 0000000000..ee2eabeb75 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/asrock/z87_pro4/board_info.txt b/src/mainboard/asrock/z87_pro4/board_info.txt new file mode 100644 index 0000000000..ab362f2236 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87%20Pro4/ +ROM protocol: SPI +Flashrom support: n +ROM package: DIP-8 (1x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87_pro4/bootblock.c b/src/mainboard/asrock/z87_pro4/bootblock.c new file mode 100644 index 0000000000..f38cf781b8 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/bootblock.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x60); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87_pro4/data.vbt b/src/mainboard/asrock/z87_pro4/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..839134bdbf0ebfb2104a8cdcfb18a78daafee4dc GIT binary patch literal 6144 zcmeHJU2GIp6h3!mc6WAmX1X0JY*(nKKww*GJ1wL(O^vhdw(gdNZht71U|3*RM2jtL zG4&^5#TxM^x-o=+A1+;ei-qfc4zj*#)V>MkPwp zv-{0CbLPx9_nv$2xp(nk`v6A6{cAhpadadFCNz{Eq3cX(kM;C#h=d2i8`|SN9V_uD z%!Qo)<`sYxV{_G}#^&bO3lr(#P+tv3``6;Ckxg5N(+!dI`12DZqnPN3VR-ZA^l*A? z<3u`z{ew@2k#lNF`;M){DO|l{+otqbD{>-=#>N%(%U2+pjSWpL4NYd_aZrjc(=_Xdvk~nkW5>wYXg!99hp~^xjALJVJU#YeI#sVJoZ}?O5(8i^C}Y6bjVAEQ zOqHdmY=vZWF)7TfYK9TX(wNlAq?BaEm{r3tE?J8uTqdC(1dRz2Ky{%-q>ID!S^ zuk`&25UDTHd@!3o(H!wJ~ZhhvpU9V3C;relEl+$INcM<@dnQ+5f z1!H0e4v7LB6BRzM|G5*88a z2#*nBgnq))ge`>agjWb}5Z)*3CmbexLimjE1>p?g0^vu3dk0+42^sL%$;>cEm*+M3 zC3vp}G6x+00mtvXO7nt5akS6TwzGswF6Z&U&D^;F zfZ!UtdqDBcf^jE9!C%z>JV2cT-Bf%;xov8`O}hpl_ogPoBq+KUnC@N&&$;WM>>cnH z2eA14f6egP#ja$!a=934sD)x-yDAQXJD7jyX)6ZZVf>d*=B}ivBHFbC7D$(PO5TMIX{8?Q65=OR05-egbV`h@e-(% z{Rl)Md|MzrV|4fklUsH|Y*&;bldu> z?WZ%xl2(DUGEf{6?#(b=hR`@PA48dne1@u;cM6m*5|vUd-kV|OvgWHZzY_U)bB4CN z_F`rk;Hx^nf+t+4WN$ zbd{3HXQ~H}^+J`|m377a=UBg!%Ac&Gh-+sfA`@|GXlD2tIC8CQD&3Ypv7CsgxP$ z&7VAZ8$_CpoZ)ZINt;2-Gq|vXUR(*nbOPs@s@cKcvhyHjX+7GRY_aFV-Pfkjnh9)g zsk4UaZjFTqWi|tqF!#OJMU4f?49rRT{pI|vd>g2mlBgwayAMp*quasV?OzH*$GT6` ziT}P_b9czHhv2O)N@k2s{A(ZqDOkq#!ez1k1i + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asrock/z87_pro4/gma-mainboard.ads b/src/mainboard/asrock/z87_pro4/gma-mainboard.ads new file mode 100644 index 0000000000..8db057db4f --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI2, -- HDMI + Analog, -- D-Sub + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87_pro4/gpio.c b/src/mainboard/asrock/z87_pro4/gpio.c new file mode 100644 index 0000000000..7423c783e5 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/gpio.c @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87_pro4/hda_verb.c b/src/mainboard/asrock/z87_pro4/hda_verb.c new file mode 100644 index 0000000000..038ad1f01f --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/hda_verb.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x18498892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18498892), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4025e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87_pro4/romstage.c b/src/mainboard/asrock/z87_pro4/romstage.c new file mode 100644 index 0000000000..9ad77c7198 --- /dev/null +++ b/src/mainboard/asrock/z87_pro4/romstage.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0140, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};