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UPSTREAM: mainboard/google/snappy: Set PL1 override to 12000mW

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Snappy is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.

BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116
Reviewed-on: https://chromium-review.googlesource.com/411424
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Wisley Chen 2016-11-10 09:44:13 -05:00 • committed by chrome-bot
commit 116911932b
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/reef/variants/snappy/devicetree.cb
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@ -49,6 +49,11 @@ chip soc/intel/apollolake
# Enable DPTF
register "dptf_enable" = "1"
# PL1 override 12000 mW: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
register "tdp_pl1_override_mw" = "12000"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"