From 10d606bfca0127c1acae8683b3ebe24dea1126aa Mon Sep 17 00:00:00 2001 From: Cliff Huang Date: Fri, 14 Nov 2025 14:22:12 -0800 Subject: [PATCH] soc/intel/common/acpi: Add P2SB write functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add common PCR write functions to write values directly to PCR registers. These functions complement the existing read and write-OR functions and provide a complete PCR access interface for ACPI code. WPCR: Generic PCR write function in the ACPI library PCRW: PCH-specific PCR write function that calls WPCR BUG=none TEST=Build test on platforms using PCR functions. Verify ACPI code can successfully write to PCR registers using the new functions. Signed-off-by: Cliff Huang Change-Id: I2c74dffda94a3ab34bd71177a3878b8d4c3119cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/90044 Tested-by: build bot (Jenkins) Reviewed-by: Jérémy Compostella Reviewed-by: Kim, Wonkyu --- src/soc/intel/common/acpi/pch_pcr.asl | 11 +++++++++++ src/soc/intel/common/acpi/pcrlib.asl | 25 +++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/src/soc/intel/common/acpi/pch_pcr.asl b/src/soc/intel/common/acpi/pch_pcr.asl index d7991c4fd1..6a791c780f 100644 --- a/src/soc/intel/common/acpi/pch_pcr.asl +++ b/src/soc/intel/common/acpi/pch_pcr.asl @@ -44,3 +44,14 @@ Method (PCRO, 3, Serialized) { OPCR(PCH_P2SB, Arg0, Arg1, Arg2) } + +/* + * Write a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to Write + */ +Method (PCRW, 3, Serialized) +{ + WPCR(PCH_P2SB, Arg0, Arg1, Arg2) +} diff --git a/src/soc/intel/common/acpi/pcrlib.asl b/src/soc/intel/common/acpi/pcrlib.asl index dd5fb9f254..65384c79d3 100644 --- a/src/soc/intel/common/acpi/pcrlib.asl +++ b/src/soc/intel/common/acpi/pcrlib.asl @@ -97,4 +97,29 @@ Method (OPCR, 4, Serialized) RPCR (Arg0, Arg1, Arg2) } +/* + * Perform PCR register write for specified Die at PID and offset + * Arg0 - Die Index + * Arg1 - PCR Port ID + * Arg2 - Register Offset + * Arg3 - Value to write + */ +Method (WPCR, 4, Serialized) +{ + OperationRegion (PCRD, SystemMemory, GPCR (Arg0, Arg1) + Arg2, 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + DATA = Arg3 + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + RPCR (Arg0, Arg1, Arg2) +} + #endif /* _SOC_INTEL_ACPI_PCR_LIB_ */