diff --git a/src/soc/intel/common/acpi/pch_pcr.asl b/src/soc/intel/common/acpi/pch_pcr.asl
index d7991c4fd1..6a791c780f 100644
--- a/src/soc/intel/common/acpi/pch_pcr.asl
+++ b/src/soc/intel/common/acpi/pch_pcr.asl
@@ -44,3 +44,14 @@ Method (PCRO, 3, Serialized)
 {
 	OPCR(PCH_P2SB, Arg0, Arg1, Arg2)
 }
+
+/*
+ * Write a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to Write
+ */
+Method (PCRW, 3, Serialized)
+{
+	WPCR(PCH_P2SB, Arg0, Arg1, Arg2)
+}
diff --git a/src/soc/intel/common/acpi/pcrlib.asl b/src/soc/intel/common/acpi/pcrlib.asl
index dd5fb9f254..65384c79d3 100644
--- a/src/soc/intel/common/acpi/pcrlib.asl
+++ b/src/soc/intel/common/acpi/pcrlib.asl
@@ -97,4 +97,29 @@ Method (OPCR, 4, Serialized)
 	RPCR (Arg0, Arg1, Arg2)
 }
 
+/*
+ * Perform PCR register write for specified Die at PID and offset
+ * Arg0 - Die Index
+ * Arg1 - PCR Port ID
+ * Arg2 - Register Offset
+ * Arg3 - Value to write
+ */
+Method (WPCR, 4, Serialized)
+{
+	OperationRegion (PCRD, SystemMemory, GPCR (Arg0, Arg1) + Arg2, 4)
+	Field (PCRD, DWordAcc, NoLock, Preserve)
+	{
+		DATA, 32
+	}
+	DATA = Arg3
+
+	/*
+	 * After every write one needs to read an innocuous register
+	 * to ensure the writes are completed for certain ports. This is done
+	 * for all ports so that the callers don't need the per-port knowledge
+	 * for each transaction.
+	 */
+	RPCR (Arg0, Arg1, Arg2)
+}
+
 #endif /* _SOC_INTEL_ACPI_PCR_LIB_ */