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treewide: Don't add bits

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Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id56310bd616cd19fee5dc934676006b2dc34b1ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65929
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2022-07-17 10:22:30 +02:00 • committed by Patrick Georgi
commit 10cd06b1c7
6 changed files with 9 additions and 9 deletions
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2
src/soc/amd/common/block/include/amdblocks/aoac.h
View file

@ -10,7 +10,7 @@
#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1)
/* Bit definitions for Device D3 Control AOACx0000[40...7E; even byte addresses] */
#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) | BIT(1))
#define FCH_AOAC_D0_UNINITIALIZED 0
#define FCH_AOAC_D0_INITIALIZED 1
#define FCH_AOAC_D1_2_3_WARM 2

2
src/soc/intel/quark/include/soc/QuarkNcSocId.h
View file

@ -807,7 +807,7 @@
#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0
#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0)
#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1)
#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1)
#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 | BIT1)
// Opcode Menu Configuration //R_OPMENU
#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58)