From 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 5 May 2014 12:42:35 -0500 Subject: [PATCH] broadwell: Add romstage usbdebug support This function will enable the EHCI port 1 on haswell/broadwell PCH to act as USB debug port. This is hardcoded to port 1. The EHCI controller must be kept enabled if CONFIG_USBDEBUG is enabled so this logic is added to the ehci ramstage driver. BUG=chrome-os-partner:28234 TEST=enable CONFIG_USBDEBUG and build+boot with USB debug output. Note that libpayload does not support usbdebug yet (I have separate patches for that) so no payload output is visible. Change-Id: I704a4786438173b2f3ee2c246636f5a24d8b428c Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/199412 Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/Makefile.inc | 6 ++++ src/soc/intel/broadwell/ehci.c | 10 ++++++ src/soc/intel/broadwell/pch.c | 4 +++ src/soc/intel/broadwell/usbdebug.c | 51 ++++++++++++++++++++++++++++ 4 files changed, 71 insertions(+) create mode 100644 src/soc/intel/broadwell/usbdebug.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 9d7ab1e8c3..88fe92fad8 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -62,6 +62,12 @@ ramstage-y += ehci.c ramstage-y += xhci.c smm-y += xhci.c +ifeq ($(CONFIG_USBDEBUG),y) +ramstage-y += usbdebug.c +romstage-y += usbdebug.c +smm-y += usbdebug.c +endif + INCLUDES += -Isrc/soc/intel/broadwell/ # Run an intermediate step when producing coreboot.rom diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index e27c8e59c9..a59d3c8190 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -26,6 +26,7 @@ #include #include #include +#include static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { @@ -70,6 +71,14 @@ static void usb_ehci_set_resources(struct device *dev) #endif } +static void ehci_enable(struct device *dev) +{ + if (CONFIG_USBDEBUG) + dev->enabled = 1; + else + pch_disable_devfn(dev); +} + static struct pci_operations ehci_ops_pci = { .set_subsystem = &usb_ehci_set_subsystem, }; @@ -79,6 +88,7 @@ static struct device_operations usb_ehci_ops = { .set_resources = &usb_ehci_set_resources, .enable_resources = &pci_dev_enable_resources, .ops_pci = &ehci_ops_pci, + .enable = &ehci_enable, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 9ac833110d..b9667cc38c 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -190,6 +190,10 @@ void broadwell_pch_enable_dev(device_t dev) if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_PCIE) return; + /* EHCI disable is handled in ramstage driver */ + if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_EHCI) + return; + if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); diff --git a/src/soc/intel/broadwell/usbdebug.c b/src/soc/intel/broadwell/usbdebug.c new file mode 100644 index 0000000000..d462e89f90 --- /dev/null +++ b/src/soc/intel/broadwell/usbdebug.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +void set_debug_port(unsigned int port) +{ + /* Hardcoded to physical port 1 */ +} + +void enable_usbdebug(unsigned int port) +{ + u32 tmp32; + + tmp32 = pci_read_config32(PCH_DEV_EHCI, PCI_VENDOR_ID); + if (tmp32 == 0xffffffff || tmp32 == 0) + return; + + /* Set the EHCI BAR address. */ + pci_write_config32(PCH_DEV_EHCI, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(PCH_DEV_EHCI, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Force ownership of the Debug Port to the EHCI controller. */ + tmp32 = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); + tmp32 |= (1 << 30); + write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, tmp32); +}