beltino: Use IT8772E SuperIO code
right now there are still a lot of traces of Chrome EC code in the beltino board. Remove them and replace them with the SuperIO code from Stumpy. BUG=none BRANCH=none TEST=boot on Beltino Change-Id: I2e4f342c5c88b3a0a3abd003a8033d1e100a1397 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/172930 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
This commit is contained in:
Stefan Reinauer
chrome-internal-fetch
parent
87687633a2
commit
0fdd60c302
8 changed files with 213 additions and 216 deletions
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@ -1,24 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* mainboard configuration */
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#include <mainboard/google/falco/ec.h>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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@ -19,92 +19,11 @@
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* MA 02110-1301 USA
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*/
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#include <mainboard/google/falco/onboard.h>
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Scope (\_SB)
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{
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Device (LID0)
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{
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Name(_HID, EisaId("PNP0C0D"))
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Method(_LID, 0)
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{
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Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
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Return (\LIDS)
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}
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}
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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}
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Device (TPAD)
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{
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Name (_ADR, 0x0)
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Name (_UID, 1)
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// Report as a Sleep Button device so Linux will
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// automatically enable it as a wake source
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Name (_HID, EisaId("PNP0C0E"))
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Name (_CRS, ResourceTemplate()
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{
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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BOARD_TRACKPAD_IRQ
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}
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VendorShort (ADDR)
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{
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BOARD_TRACKPAD_I2C_ADDR
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}
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})
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Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
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Method (_DSW, 3, NotSerialized)
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{
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Store (BOARD_TRACKPAD_WAKE_GPIO, Local0)
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If (LEqual (Arg0, 1)) {
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// Enable GPIO as wake source
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\_SB.PCI0.LPCB.GWAK (Local0)
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}
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}
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}
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Device (TSCR)
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{
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Name (_ADR, 0x0)
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Name (_UID, 2)
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// Report as a Sleep Button device so Linux will
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// automatically enable it as a wake source
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Name (_HID, EisaId("PNP0C0E"))
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Name (_CRS, ResourceTemplate()
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{
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Interrupt (ResourceConsumer, Edge, ActiveLow)
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{
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BOARD_TOUCHSCREEN_IRQ
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}
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VendorShort (ADDR)
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{
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BOARD_TOUCHSCREEN_I2C_ADDR
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}
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})
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Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
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Method (_DSW, 3, NotSerialized)
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{
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Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0)
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If (LEqual (Arg0, 1)) {
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// Enable GPIO as wake source
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\_SB.PCI0.LPCB.GWAK (Local0)
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}
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}
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}
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}
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@ -68,19 +68,5 @@ Method(_PTS,1)
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Method(_WAK,1)
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{
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/* Update AC status */
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Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
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if (LNotEqual (Local0, \PWRS)) {
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Store (Local0, \PWRS)
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Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
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}
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/* Update LID status */
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Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
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if (LNotEqual (Local0, \LIDS)) {
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Store (Local0, \LIDS)
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Notify (\_SB.LID0, 0x80)
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}
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Return(Package(){0,0})
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}
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@ -17,13 +17,20 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* mainboard configuration */
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#include <mainboard/google/falco/ec.h>
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/* Values should match those defined in devicetree.cb */
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#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
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#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
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#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
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#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
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#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
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#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
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#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard
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#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse
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#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1
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#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
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#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
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#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
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#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
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#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
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#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
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#include "superio/ite/it8772f/acpi/superio.asl"
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,20 +21,6 @@
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Scope (\_TZ)
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{
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// Handler for throttle requests on this platform
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// 0 = Stop throttling
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// 1 = Start throttling
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Method (THRT, 1, Serialized)
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{
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If (LEqual (Arg0, 0)) {
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/* Disable Power Limit */
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\_SB.PCI0.MCHC.CTLD ()
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} Else {
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/* Enable Power Limit */
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\_SB.PCI0.MCHC.CTLE (\F0PW)
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}
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}
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ThermalZone (THRM)
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{
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Name (_TC1, 0x02)
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@ -77,35 +63,211 @@ Scope (\_TZ)
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Method (_TMP, 0, Serialized)
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{
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// Get Temperature from TIN# set in NVS
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Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
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// Get CPU Temperature from PECI via SuperIO TMPIN3
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Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
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// Check for sensor not calibrated
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If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) {
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Return (CTOK(0))
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// Check for invalid readings
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If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
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Return (CTOK (\F2ON))
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}
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// Check for sensor not present
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If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
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Return (CTOK(0))
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// PECI raw value is an offset from Tj_max
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Subtract (255, Local0, Local1)
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// Handle values greater than Tj_max
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If (LGreaterEqual (Local1, \TMAX)) {
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Return (CTOK (\TMAX))
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}
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// Check for sensor not powered
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If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
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Return (CTOK(0))
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// Subtract from Tj_max to get temperature
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Subtract (\TMAX, Local1, Local0)
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Return (CTOK (Local0))
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}
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Method (_AC0) {
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If (LLessEqual (\FLVL, 0)) {
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Return (CTOK (\F0OF))
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} Else {
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Return (CTOK (\F0ON))
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}
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}
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// Check for sensor bad reading
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If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
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Return (CTOK(0))
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Method (_AC1) {
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If (LLessEqual (\FLVL, 1)) {
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Return (CTOK (\F1OF))
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} Else {
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Return (CTOK (\F1ON))
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}
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}
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// Adjust by offset to get Kelvin
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Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
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Method (_AC2) {
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If (LLessEqual (\FLVL, 2)) {
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Return (CTOK (\F2OF))
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} Else {
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Return (CTOK (\F2ON))
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}
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}
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// Convert to 1/10 Kelvin
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Multiply (Local0, 10, Local0)
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Return (Local0)
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Method (_AC3) {
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If (LLessEqual (\FLVL, 3)) {
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Return (CTOK (\F3OF))
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} Else {
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Return (CTOK (\F3ON))
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}
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}
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Method (_AC4) {
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If (LLessEqual (\FLVL, 4)) {
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Return (CTOK (\F4OF))
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} Else {
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Return (CTOK (\F4ON))
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}
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}
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Name (_AL0, Package () { FAN0 })
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Name (_AL1, Package () { FAN1 })
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Name (_AL2, Package () { FAN2 })
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Name (_AL3, Package () { FAN3 })
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Name (_AL4, Package () { FAN4 })
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PowerResource (FNP0, 0, 0)
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{
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Method (_STA) {
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If (LLessEqual (\FLVL, 0)) {
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Return (One)
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} Else {
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Return (Zero)
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}
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}
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Method (_ON) {
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Store (0, \FLVL)
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Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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Method (_OFF) {
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Store (1, \FLVL)
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Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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PowerResource (FNP1, 0, 0)
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{
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Method (_STA) {
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If (LLessEqual (\FLVL, 1)) {
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Return (One)
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} Else {
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Return (Zero)
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}
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}
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Method (_ON) {
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Store (1, \FLVL)
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Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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Method (_OFF) {
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Store (2, \FLVL)
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Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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PowerResource (FNP2, 0, 0)
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{
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Method (_STA) {
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If (LLessEqual (\FLVL, 2)) {
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Return (One)
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} Else {
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Return (Zero)
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}
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}
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Method (_ON) {
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Store (2, \FLVL)
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Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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Method (_OFF) {
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Store (3, \FLVL)
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Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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PowerResource (FNP3, 0, 0)
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{
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Method (_STA) {
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If (LLessEqual (\FLVL, 3)) {
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Return (One)
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} Else {
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Return (Zero)
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}
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}
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Method (_ON) {
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Store (3, \FLVL)
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Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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Method (_OFF) {
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Store (4, \FLVL)
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Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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PowerResource (FNP4, 0, 0)
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{
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Method (_STA) {
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If (LLessEqual (\FLVL, 4)) {
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Return (One)
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} Else {
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Return (Zero)
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}
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}
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Method (_ON) {
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Store (4, \FLVL)
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Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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Method (_OFF) {
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Store (4, \FLVL)
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Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
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Notify (\_TZ.THRM, 0x81)
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}
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}
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Device (FAN0)
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{
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Name (_HID, EISAID ("PNP0C0B"))
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Name (_UID, 0)
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Name (_PR0, Package () { FNP0 })
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}
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Device (FAN1)
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{
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Name (_HID, EISAID ("PNP0C0B"))
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Name (_UID, 1)
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Name (_PR0, Package () { FNP1 })
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}
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Device (FAN2)
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{
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Name (_HID, EISAID ("PNP0C0B"))
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Name (_UID, 2)
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Name (_PR0, Package () { FNP2 })
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}
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Device (FAN3)
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{
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Name (_HID, EISAID ("PNP0C0B"))
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Name (_UID, 3)
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Name (_PR0, Package () { FNP3 })
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}
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Device (FAN4)
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{
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Name (_HID, EISAID ("PNP0C0B"))
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Name (_UID, 4)
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Name (_PR0, Package () { FNP4 })
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}
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}
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}
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@ -106,24 +106,12 @@ chip northbridge/intel/haswell
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip superio/ite/it8772f
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# Enable GPIO10 as USBPWRON12#
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# Enable GPIO12 as USBPWRON13#
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register "gpio_set1" = "0x05"
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# Enable GPIO22 as SIO_WAEKSCI#
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register "gpio_set2" = "0x04"
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# Enable GPIO32 as SIO_EXTSMI#
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register "gpio_set3" = "0x04"
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# Enable GPIO45 as LED_POWER#
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register "gpio_set4" = "0x20"
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# Enable GPIO51 as USBPWRON8#
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# Enable GPIO52 as USBPWRON1#
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register "gpio_set5" = "0x06"
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# Skip keyboard init
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register "skip_keyboard" = "1"
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# Enable PECI on TMPIN3
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register "peci_tmpin" = "3"
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# Enable FAN3
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register "fan3_enable" = "1"
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# Enable FAN2
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register "fan2_enable" = "1"
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device pnp 2e.0 off end # FDC
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device pnp 2e.1 on # Serial Port 1
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@ -36,7 +36,6 @@
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#include <boot/coreboot_tables.h>
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#include "hda_verb.h"
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#include <southbridge/intel/lynxpoint/pch.h>
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#include "onboard.h"
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void mainboard_suspend_resume(void)
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{
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|
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|
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@ -1,40 +0,0 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef ONBOARD_H
|
||||
#define ONBOARD_H
|
||||
|
||||
#define BOARD_LIGHTSENSOR_NAME "lightsensor"
|
||||
#define BOARD_LIGHTSENSOR_IRQ 51 /* PIRQT */
|
||||
#define BOARD_LIGHTSENSOR_I2C_BUS 2 /* I2C1 */
|
||||
#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44
|
||||
|
||||
#define BOARD_TRACKPAD_NAME "trackpad"
|
||||
#define BOARD_TRACKPAD_IRQ 37 /* PIRQV */
|
||||
#define BOARD_TRACKPAD_WAKE_GPIO 12 /* GPIO12 */
|
||||
#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */
|
||||
#define BOARD_TRACKPAD_I2C_ADDR 0x67
|
||||
|
||||
#define BOARD_TOUCHSCREEN_NAME "touchscreen"
|
||||
#define BOARD_TOUCHSCREEN_IRQ 38 /* PIRQW */
|
||||
#define BOARD_TOUCHSCREEN_WAKE_GPIO 25 /* GPIO25 */
|
||||
#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */
|
||||
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue