From 0fd6a83a1164a27361650bb73c0cc3fab6ec49cc Mon Sep 17 00:00:00 2001 From: Qinghong Zeng Date: Fri, 30 Jan 2026 16:40:57 +0800 Subject: [PATCH] mb/google/nissa/var/rull: Support x32 memory configuration Use GPP_E19 level to determine whether x32 memory configuration is supported. BUG=b:480003949 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I68d9060686f6b48c2fd7a296cd78346233265e24 Signed-off-by: Qinghong Zeng Reviewed-on: https://review.coreboot.org/c/coreboot/+/91003 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Eric Lai --- src/mainboard/google/brya/Kconfig | 1 + .../google/brya/variants/rull/Makefile.mk | 1 + .../google/brya/variants/rull/gpio.c | 5 +++++ .../google/brya/variants/rull/memory.c | 19 +++++++++++++++++++ 4 files changed, 26 insertions(+) create mode 100644 src/mainboard/google/brya/variants/rull/memory.c diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index e1d64876c5..39d88156bb 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -605,6 +605,7 @@ config BOARD_GOOGLE_RULL select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_GPIO_KEYS + select ENFORCE_MEM_CHANNEL_DISABLE select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE diff --git a/src/mainboard/google/brya/variants/rull/Makefile.mk b/src/mainboard/google/brya/variants/rull/Makefile.mk index f41cdfdb8a..efe5002383 100644 --- a/src/mainboard/google/brya/variants/rull/Makefile.mk +++ b/src/mainboard/google/brya/variants/rull/Makefile.mk @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/rull/gpio.c b/src/mainboard/google/brya/variants/rull/gpio.c index 24096d73bc..0c5c2d0552 100644 --- a/src/mainboard/google/brya/variants/rull/gpio.c +++ b/src/mainboard/google/brya/variants/rull/gpio.c @@ -90,6 +90,9 @@ static const struct pad_config override_gpio_table[] = { /* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */ PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ /* BT_I2S_BCLK */ PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), @@ -138,6 +141,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), }; static const struct pad_config romstage_gpio_table[] = { diff --git a/src/mainboard/google/brya/variants/rull/memory.c b/src/mainboard/google/brya/variants/rull/memory.c new file mode 100644 index 0000000000..0608ae7e0d --- /dev/null +++ b/src/mainboard/google/brya/variants/rull/memory.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E19 High -> One RAM Chip + * GPP_E19 Low -> Two RAM Chip + * Disable all other channels except first two on each controller + */ + if (gpio_get(GPP_E19)) + return (BIT(2) | BIT(3)); + + return 0; +}