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UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE

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Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.

As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.

There are no reasons to have this as board-specific setting.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Reviewed-on: https://chromium-review.googlesource.com/422239
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-12-09 17:43:27 +02:00 • committed by chrome-bot
commit 0faab9ae82
15 changed files with 20 additions and 56 deletions
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2
src/northbridge/intel/nehalem/Kconfig
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@ -39,7 +39,7 @@ config VGA_BIOS_ID
config DCACHE_RAM_BASE
hex
default 0xff7f0000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex