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Hopefully this is my last commit of major infrasture changes for a while.

Browse source 
Highlights:
 - elfboot.c Now can load images to the ram location where linuxBIOS is running
 - Added the standalone directory for bootloaders built from the linuxBIOS source

Other things:
- Correctly maode fallback_boot.c conditional
- Added entry32.lds to do the math for segment descriptor table entries
- Merged ldscript.cacheram and ldscript.base
- Moved assembly code to the sections .rom.text and .rom.data
- Modified linuxBIOS so C code completely runs from RAM as the SiS630
  case does
- Updated and commented example config files for the supermicro p4dc6
- Bumped the elfboot loader version to 1.0
- Removed extra carriage returns in dump_northbridge.inc (DOS->UNIX)
- General cleanups to the config of the supermicro p4dc6
This commit is contained in:
Eric W. Biederman 2002-01-16 05:54:23 +00:00
commit 0f7f76fb40
56 changed files with 1191 additions and 375 deletions
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6
src/cpu/i386/entry16.inc
View file

@ -25,7 +25,7 @@ it with the version available from LANL.
* protected mode.
*/
.text
/* .section ".rom.text" */
.code16
.globl EXT(_start)
.type EXT(_start), @function
@ -102,8 +102,8 @@ EXT(_start):
.align 4
.globl EXT(gdtptr16)
EXT(gdtptr16):
.word 4*8-1
.long gdt /* we know the offset */
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
.globl EXT(_estart)
EXT(_estart):

18
src/cpu/i386/entry32.inc
View file

@ -2,7 +2,7 @@
#include <arch/cache_ram.h>
.text
/* .section ".rom.text" */
.code32
/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
@ -16,16 +16,16 @@
.align 4
.globl EXT(gdtptr)
EXT(gdtptr):
.word 4*8-1
.long gdt /* we know the offset */
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
gdt:
.word 0x0000, 0x0000 /* dummy */
.byte 0x00, 0x00, 0x00, 0x00
.word 0xffff, (CACHE_RAM_SEG_BASE & 0xffff) /* flat offset data segment */
.byte ((CACHE_RAM_SEG_BASE >> 16)& 0xff), 0x93, 0xcf
.byte ((CACHE_RAM_SEG_BASE >> 24) & 0xff)
.word 0xffff, _cache_ram_seg_base_low /* flat cache ram offset data segment */
.byte _cache_ram_seg_base_middle, 0x93, 0xcf
.byte _cache_ram_seg_base_high
.word 0xffff, 0x0000 /* flat code segment */
.byte 0x00, 0x9b, 0xcf, 0x00
@ -33,6 +33,12 @@ gdt:
.word 0xffff, 0x0000 /* flat data segment */
.byte 0x00, 0x93, 0xcf, 0x00
.word 0xffff, _rom_code_seg_base_low /* flat rom offset code segment */
.byte _rom_code_seg_base_middle, 0x9b, 0xcf
.byte _rom_code_seg_base_high
gdt_end:
/*
* When we come here we are in protected mode. We expand
* the stack and copies the data segment from ROM to the

12
src/cpu/i386/entry32.lds Normal file
View file

@ -0,0 +1,12 @@
_cache_ram_seg_base = DEFINED(CACHE_RAM_BASE)? CACHE_RAM_BASE - _rodata : 0;
_cache_ram_seg_base_low = (_cache_ram_seg_base) & 0xffff;
_cache_ram_seg_base_middle = (_cache_ram_seg_base >> 16) & 0xff;
_cache_ram_seg_base_high = (_cache_ram_seg_base >> 24) & 0xff;
_rom_code_seg_base = _ltext - _text;
_rom_code_seg_base_low = (_rom_code_seg_base) & 0xffff;
_rom_code_seg_base_middle = (_rom_code_seg_base >> 16) & 0xff;
_rom_code_seg_base_high = (_rom_code_seg_base >> 24) & 0xff;

3
src/cpu/i786/cache_ram.lds Normal file
View file

@ -0,0 +1,3 @@
_clrodata = _lrodata - _cache_ram_seg_base;
_celdata = _eldata - _cache_ram_seg_base;
___cache_ram_code_start = __cache_ram_code_start - _rom_code_seg_base;

24
src/cpu/i786/cache_ram_start.inc
View file

@ -1,9 +1,9 @@
#include <arch/cache_ram.h>
/* copy data segment from FLASH ROM to CACHE */
movl $(EXT(_ldata) - CACHE_RAM_SEG_BASE), %esi
movl $EXT(_data), %edi
movl $(EXT(_eldata) - CACHE_RAM_SEG_BASE), %ecx
movl $_clrodata, %esi
movl $_rodata, %edi
movl $_celdata, %ecx
subl %esi, %ecx
jz 1f /* should not happen */
rep
@ -23,5 +23,21 @@
/* set new stack */
movl $(_stack + STACK_SIZE), %esp
call cache_ram_start
/* The next bit is tricky.
* - I change code segments to handle the cache ram case.
* - I force the rom_code code segment again
* when I call cache_ram_start to avoid strange processor
* behavoir. A simple call instruction does not work at
* this point. This is due either to virutally mapped
* instruction caches, or address wrap around.
* - I change teh code segments back to my normal segment with
* a 4GB limit and a base address of 0.
*/
ljmp $0x20, $___cache_ram_code_start
.globl __cache_ram_code_start
__cache_ram_code_start:
lcall $0x20, $cache_ram_start
ljmp $0x10, $__cache_ram_code_done
.globl __cache_ram_code_done
__cache_ram_code_done: