From 0ef4bd807cef488d5be236643af9ca07bfedb1d2 Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Mon, 17 Nov 2025 15:51:28 +0800 Subject: [PATCH] mb/google/ocelot/var/ocelot: Update DDR5 memory configs This change updates memory configuration for DDR5. 1. Set SaGv frequencies 2. Configure gear settings 3. Map Channel/PHY clock Bug=b:452542491 TEST=Build kodkod image. Change-Id: I49939c8bde06b4a3148b48307b4ccbebf8ba560d Signed-off-by: Ian Feng Reviewed-on: https://review.coreboot.org/c/coreboot/+/90070 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- .../google/ocelot/variants/kodkod/Makefile.mk | 2 + .../google/ocelot/variants/kodkod/memory.c | 4 ++ .../google/ocelot/variants/kodkod/variant.c | 41 +++++++++++++++++++ 3 files changed, 47 insertions(+) create mode 100644 src/mainboard/google/ocelot/variants/kodkod/variant.c diff --git a/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk b/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk index 4c33dad4db..1e3790a9f1 100644 --- a/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk +++ b/src/mainboard/google/ocelot/variants/kodkod/Makefile.mk @@ -3,4 +3,6 @@ bootblock-y += gpio.c romstage-y += gpio.c romstage-y += memory.c +romstage-y += variant.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/ocelot/variants/kodkod/memory.c b/src/mainboard/google/ocelot/variants/kodkod/memory.c index f9e6fedfe4..06a9858c4b 100644 --- a/src/mainboard/google/ocelot/variants/kodkod/memory.c +++ b/src/mainboard/google/ocelot/variants/kodkod/memory.c @@ -17,6 +17,10 @@ static const struct mb_cfg ddr5_mem_config = { .ddr_config = { .dq_pins_interleaved = false, }, + + .rcomp = { + .resistor = 100, + }, }; const struct mb_cfg *variant_memory_params(void) { diff --git a/src/mainboard/google/ocelot/variants/kodkod/variant.c b/src/mainboard/google/ocelot/variants/kodkod/variant.c new file mode 100644 index 0000000000..c667edcccf --- /dev/null +++ b/src/mainboard/google/ocelot/variants/kodkod/variant.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void variant_update_soc_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; + + /* Override FSP-M SaGv frequency and gear for DDR5 boards */ + m_cfg->SaGvFreq[0] = 3200; + m_cfg->SaGvGear[0] = GEAR_4; + + m_cfg->SaGvFreq[1] = 4800; + m_cfg->SaGvGear[1] = GEAR_4; + + m_cfg->SaGvFreq[2] = 5600; + m_cfg->SaGvGear[2] = GEAR_4; + + m_cfg->SaGvFreq[3] = 6400; + m_cfg->SaGvGear[3] = GEAR_4; + + /* + * Override FSP-M ChannelToCkdQckMapping to map memory channels + * to Clock Driver (CKD) and Query Clock (QCK) signals. + */ + + const uint8_t channel_to_ckd_qck[] = { 1, 0, 0, 0, + 0, 0, 0, 0 }; + memcpy(m_cfg->ChannelToCkdQckMapping, channel_to_ckd_qck + , sizeof(channel_to_ckd_qck)); + + /* + * Override FSP-M PhyClockToCkdDimm to map PHY clocks + * to Clock Driver DIMM connections. + */ + const uint8_t phy_clock_to_ckd_dimm[] = { 4, 0, 4, 0, + 0, 0, 0, 0 }; + memcpy(m_cfg->PhyClockToCkdDimm, phy_clock_to_ckd_dimm, + sizeof(phy_clock_to_ckd_dimm)); +}