From 0e9d85425e141c756fe7d758cb16d395b6b94ec7 Mon Sep 17 00:00:00 2001 From: Ivy Jian Date: Wed, 26 Nov 2025 08:49:37 +0800 Subject: [PATCH] mb/google/ocelot/var/matsu: Fix GPP_V3 internal pull-up configuration According to doc#836031, GPP_V3 defaults to Native F1 with the integrated pull-up enabled. However, coreboot was configuring this pin with the internal pull-up set to NONE, which disabled the pull-up and caused GPP_V3/PWRBTN# to read low, leading to unexpected shutdowns. Update the pad configuration to use the internal pull-up. BUG=b:463193164 TEST=boots normally and no unexpected shutdown occurs. Change-Id: Ia650aa9b60d7ce634827330954b1a9c9ac3d7567 Signed-off-by: Ivy Jian Reviewed-on: https://review.coreboot.org/c/coreboot/+/90218 Reviewed-by: Bob Moragues Reviewed-by: Pranava Y N Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/google/ocelot/variants/matsu/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/ocelot/variants/matsu/gpio.c b/src/mainboard/google/ocelot/variants/matsu/gpio.c index abbf708ffd..7bca115efd 100644 --- a/src/mainboard/google/ocelot/variants/matsu/gpio.c +++ b/src/mainboard/google/ocelot/variants/matsu/gpio.c @@ -339,7 +339,7 @@ static const struct pad_config gpio_table[] = { /* GPP_V02: LANWAKE_N_R */ PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), /* GPP_V03: PWRBTN_MCP_N */ - PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), /* GPP_V04: PM_SLP_S3_N */ PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* GPP_V05: PM_SLP_S4_N */