Drop duplicated functions from W83627THG SuperI/O stage1 code and fix
up a function prototype. Fix up #include statements for W83627THG SuperI/O stage2 code. Use anonymous instead of named unions in struct device. Point pnp_dev_info members to w83627thg_ops. Disable UART and keyboard initialization for now. Add new code in phase3_chip_setup_dev to fill in configuration values from the dts (code is partially disabled). Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1032 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger
parent
3e6f0c2245
commit
0df280f294
2 changed files with 95 additions and 41 deletions
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@ -21,25 +21,12 @@
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#include <device/pnp.h>
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#include "w83627thg.h"
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static inline void pnp_enter_ext_func_mode(device_t dev)
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static void w83627thg_enable_serial(u8 dev, u8 serial, u16 iobase)
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{
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unsigned int port = dev >> 8;
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outb(0x87, port);
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outb(0x87, port);
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}
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static void pnp_exit_ext_func_mode(device_t dev)
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{
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unsigned int port = dev >> 8;
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outb(0xaa, port);
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}
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static void w83627thg_enable_serial(device_t dev, unsigned int iobase)
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{
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pnp_enter_ext_func_mode(dev);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
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pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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pnp_set_enable(dev, 1);
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pnp_exit_ext_func_mode(dev);
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rawpnp_enter_ext_func_mode(dev);
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rawpnp_set_logical_device(dev, serial);
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rawpnp_set_enable(dev, 0);
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rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase);
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rawpnp_set_enable(dev, 1);
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rawpnp_exit_ext_func_mode(dev);
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}
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@ -30,16 +30,16 @@
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#include <keyboard.h>
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// #include <pc80/mc146818rtc.h>
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#include <statictree.h>
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#include "w83627hf.h"
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#include "w83627thg.h"
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static void w83627thg_enter_ext_func_mode(struct device * dev)
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{
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outb(0x87, dev->path.u.pnp.port);
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outb(0x87, dev->path.u.pnp.port);
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outb(0x87, dev->path.pnp.port);
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outb(0x87, dev->path.pnp.port);
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}
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static void w83627thg_exit_ext_func_mode(struct device * dev)
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{
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outb(0xaa, dev->path.u.pnp.port);
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outb(0xaa, dev->path.pnp.port);
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}
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static void w83627thg_init(struct device * dev)
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@ -53,19 +53,19 @@ static void w83627thg_init(struct device * dev)
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return;
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}
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conf = dev->device_configuration;
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switch(dev->path.u.pnp.device) {
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switch(dev->path.pnp.device) {
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case W83627THG_SP1:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com1);
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// init_uart8250(res0->base, &conf->com1);
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break;
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case W83627THG_SP2:
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res0 = find_resource(dev, PNP_IDX_IO0);
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init_uart8250(res0->base, &conf->com2);
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// init_uart8250(res0->base, &conf->com2);
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break;
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case W83627THG_KBC:
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res0 = find_resource(dev, PNP_IDX_IO0);
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res1 = find_resource(dev, PNP_IDX_IO1);
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init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
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// init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
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break;
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}
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}
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@ -92,31 +92,98 @@ static void w83627thg_enable(struct device * dev)
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}
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static void phase3_chip_setup_dev(struct device *dev);
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static struct device_operations w83627thg_ops = {
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struct device_operations w83627thg_ops = {
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.phase3_chip_setup_dev = phase3_chip_setup_dev,
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.phase3_enable = w83627thg_enable,
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.phase4_read_resources = pnp_read_resources,
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.phase4_set_resources = w83627thg_set_resources,
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.phase5_enable_resources = w83627thg_enable_resources,
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.enable = ,
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.init = w83627thg_init,
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.phase6_init = w83627thg_init,
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};
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/* TODO: this device is not at all filled out. Just copied from v2. */
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static struct pnp_info pnp_dev_info[] = {
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{ &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
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{ &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
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{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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{ &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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{ &w83627thg_ops, W83627THG_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
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{ &w83627thg_ops, W83627THG_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
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{ &w83627thg_ops, W83627THG_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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{ &w83627thg_ops, W83627THG_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
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// No 4 { 0,},
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{ &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
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{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
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{ &ops, W83627THG_GPIO2,},
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{ &ops, W83627THG_GPIO3,},
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{ &ops, W83627THG_ACPI, PNP_IRQ0, },
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{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
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{ &w83627thg_ops, W83627THG_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
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{ &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
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{ &w83627thg_ops, W83627THG_GPIO2,},
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{ &w83627thg_ops, W83627THG_GPIO3,},
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{ &w83627thg_ops, W83627THG_ACPI, 0, PNP_IRQ0, },
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{ &w83627thg_ops, W83627THG_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
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};
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static void phase3_chip_setup_dev(struct device *dev)
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{
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/* Get dts values and populate pnp_dev_info. */
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const struct superio_winbond_w83627thg_dts_config * const conf = dev->device_configuration;
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#if 0
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These are not set up at all v2. Ignore for now. */
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/* Floppy */
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pnp_dev_info[W83627THG_FDC].enable = conf->floppyenable;
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pnp_dev_info[W83627THG_FDC].io0.val = conf->floppyio;
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pnp_dev_info[W83627THG_FDC].irq0.val = conf->floppyirq;
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pnp_dev_info[W83627THG_FDC].drq0.val = conf->floppydrq;
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/* Parallel port */
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pnp_dev_info[W83627THG_PP].enable = conf->ppenable;
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pnp_dev_info[W83627THG_PP].io0.val = conf->ppio;
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pnp_dev_info[W83627THG_PP].irq0.val = conf->ppirq;
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/* Consumer IR */
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pnp_dev_info[W83627THG_CIR].enable = conf->cirenable;
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/* Game port */
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pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].enable = conf->gameenable;
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pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io0.val = conf->gameio;
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pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io1.val = conf->gameio2;
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pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0.val = conf->gameirq;
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/* GPIO2 */
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pnp_dev_info[W83627THG_GPIO2].enable = conf->gpio2enable;
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/* GPIO3 */
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pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio3enable;
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/* ACPI */
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pnp_dev_info[W83627THG_ACPI].enable = conf->acpienable;
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/* Hardware Monitor */
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pnp_dev_info[W83627THG_HWM].enable = conf->hwmenable;
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pnp_dev_info[W83627THG_HWM].io0.val = conf->hwmio;
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pnp_dev_info[W83627THG_HWM].irq0.val = conf->hwmirq;
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#endif
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/* COM1 */
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pnp_dev_info[W83627THG_SP1].enable = conf->com1enable;
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pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io;
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pnp_dev_info[W83627THG_SP1].irq0.val = conf->com1irq;
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/* COM2 */
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pnp_dev_info[W83627THG_SP2].enable = conf->com2enable;
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pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io;
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pnp_dev_info[W83627THG_SP2].irq0.val = conf->com2irq;
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/* Keyboard */
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pnp_dev_info[W83627THG_KBC].enable = conf->kbenable;
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pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio;
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pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2;
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pnp_dev_info[W83627THG_KBC].irq0.val = conf->kbirq;
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pnp_dev_info[W83627THG_KBC].irq1.val = conf->kbirq2;
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/* Initialize SuperIO for PNP children. */
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if (!dev->links) {
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dev->links = 1;
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dev->link[0].dev = dev;
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dev->link[0].children = NULL;
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dev->link[0].link = 0;
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}
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/* Call init with updated tables to create children. */
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pnp_enable_devices(dev, &w83627thg_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
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}
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