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mb/google/brya/anahera{4es}: Correct SSD power sequence

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M.2 spec describes PERST# should be sequenced after power enable.

BUG=b:213021171
TEST=FW_NAME=redrix emerge-brya coreboot

Change-Id: I66345d985f4db4f13b23c0a21c179835908b6574
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Wisley Chen 2021-12-29 11:18:52 +06:00 • committed by Felix Held
commit 0de3e6570e
4 changed files with 36 additions and 2 deletions
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2
src/mainboard/google/brya/variants/anahera/Makefile.inc
View file

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

17
src/mainboard/google/brya/variants/anahera/gpio.c
View file

@ -128,12 +128,23 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/*
* enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and
* then deassert PERST# in romstage
*/
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_MMC */
PAD_CFG_GPO(GPP_E20, 1, DEEP),
};
static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
@ -145,3 +156,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

2
src/mainboard/google/brya/variants/anahera4es/Makefile.inc
View file

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-y += gpio.c
ramstage-$(CONFIG_FW_CONFIG) += fw_config.c

17
src/mainboard/google/brya/variants/anahera4es/gpio.c
View file

@ -128,12 +128,23 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/*
* enable EN_PP3300_SSD in bootblock, then PERST# is asserted, and
* then deassert PERST# in romstage
*/
/* H13 : I2C7_SCL ==> EN_PP3300_SD */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_MMC */
PAD_CFG_GPO(GPP_E20, 1, DEEP),
};
static const struct pad_config romstage_gpio_table[] = {
/* B4 : PROC_GP3 ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_B4, 1, DEEP),
};
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = ARRAY_SIZE(override_gpio_table);
@ -145,3 +156,9 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}