From 0dac2ad3aaa01185ce94fdd0c07e222bbf02b7c0 Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Tue, 10 Sep 2024 20:07:16 +0800
Subject: [PATCH] soc/intel/xeon_sp: Support GNR PCIe root ports

Add device IDs for GNR PCIe root ports so that these devices can
be supported by the Xeon-SP PCIe root port driver.

Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84311
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/xeon_sp/pcie_root_port.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/intel/xeon_sp/pcie_root_port.c b/src/soc/intel/xeon_sp/pcie_root_port.c
index fb9abde131..6ecbcecb59 100644
--- a/src/soc/intel/xeon_sp/pcie_root_port.c
+++ b/src/soc/intel/xeon_sp/pcie_root_port.c
@@ -69,6 +69,14 @@ static const unsigned short pcie_root_port_ids[] = {
 	0x352c,
 	0x352d,
 	0x347a,
+	0x0db0,
+	0x0db1,
+	0x0db2,
+	0x0db3,
+	0x0db6,
+	0x0db7,
+	0x0db8,
+	0x0db9,
 	0
 };