From 0d25a27f300acc4b65a894110d3ee0cc9676cd12 Mon Sep 17 00:00:00 2001
From: Jitao Shi <jitao.shi@mediatek.com>
Date: Fri, 15 Jul 2016 14:23:53 +0800
Subject: [PATCH] mt8173: dsi: set mipi pin driving control on

We set this driving control to prevent signal attenuation caused by
LVDS DRV termination.

When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV
termination status is unknown(floating). And there is a chance that MIPI
output would be influence. The DSI's LP signal will be half voltage
attenuation. There will be no display on panel.

When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination would be
effective and termination is fixed OFF. The DSI won't be influence.

We only need to set this register once. So we set it here to prevent
repeat setting in the kernel when the system goes to recovery mode.

BUG=chrome-os-partner:55296
BRANCH=none
TEST=build pass elm and show ui

Change-Id: Ie71f9cc41924787be8539c576392034320b57a49
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/360850
Commit-Ready: jitao shi <jitao.shi@mediatek.com>
Tested-by: jitao shi <jitao.shi@mediatek.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
 src/mainboard/google/oak/mainboard.c      |  4 ++++
 src/soc/mediatek/mt8173/dsi.c             | 19 +++++++++++++++++
 src/soc/mediatek/mt8173/include/soc/dsi.h | 26 +++++++++++++++++++++++
 3 files changed, 49 insertions(+)

diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c
index 1bf8d49872..e33d08c7a1 100644
--- a/src/mainboard/google/oak/mainboard.c
+++ b/src/mainboard/google/oak/mainboard.c
@@ -252,6 +252,10 @@ static void mainboard_init(device_t dev)
 	gpio_input(PAD_EINT1); /* SD_DET */
 
 	configure_audio();
+
+	/* fix dsi lp mode is half voltage attenuation */
+	mtk_dsi_pin_drv_ctrl();
+
 	if (display_init_required()) {
 		configure_backlight();
 		configure_display();
diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c
index 1d195719b0..6a4d8d7c3b 100644
--- a/src/soc/mediatek/mt8173/dsi.c
+++ b/src/soc/mediatek/mt8173/dsi.c
@@ -20,6 +20,7 @@
 #include <soc/i2c.h>
 #include <soc/gpio.h>
 #include <soc/dsi.h>
+#include <timer.h>
 
 static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes,
 				   const struct edid *edid)
@@ -298,3 +299,21 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes,
 
 	return 0;
 }
+
+void mtk_dsi_pin_drv_ctrl(void)
+{
+	struct stopwatch sw;
+
+	setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON);
+
+	stopwatch_init_usecs_expire(&sw, 1000);
+
+	do {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR, "enable lvdstx_power fail!!!\n");
+			return;
+		}
+	} while ((read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK) == 0);
+
+	clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN);
+}
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h
index 1abbd78ae9..73f4425684 100644
--- a/src/soc/mediatek/mt8173/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8173/include/soc/dsi.h
@@ -263,7 +263,33 @@ enum {
 	RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8)
 };
 
+/* LVDS_TX1_REG */
+struct lvds_tx1_regs {
+	u32 lvdstx1_ctl1;
+	u32 lvdstx1_ctl2;
+	u32 lvdstx1_ctl3;
+	u32 lvdstx1_ctl4;
+	u32 lvdstx1_ctl5;
+	u32 vopll_ctl1;
+	u32 vopll_ctl2;
+	u32 vopll_ctl3;
+};
+
+static struct lvds_tx1_regs * const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800);
+
+/* LVDS_VOPLL_CTRL3 */
+enum {
+	RG_LVDSTX_21EDG = BIT(0),
+	RG_LVDSTX_21LEV = BIT(1),
+	RG_LVDSTX_51EDG = BIT(2),
+	RG_LVDSTX_51LEV = BIT(3),
+	RG_AD_LVDSTX_PWR_ACK = BIT(4),
+	RG_DA_LVDS_ISO_EN = BIT(8),
+	RG_DA_LVDSTX_PWR_ON = BIT(9)
+};
+
 int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes,
 		 const struct edid *edid);
+void mtk_dsi_pin_drv_ctrl(void);
 
 #endif