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mb/google/hatch: Remove fixed IccMax values

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Remove fixed IccMax values for all domains.
IccMax will be selected by CPU SKU in
fill_vr_domain_config function.

BUG=b:145094963
BRANCH=None
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to device and checked the log.

Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Jamie Chen 2020-01-07 15:31:00 +08:00 • committed by Edward O'Callaghan
commit 0c89c297e6
1 changed files with 7 additions and 4 deletions
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11
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -58,6 +58,9 @@ chip soc/intel/cannonlake
register "PmTimerDisabled" = "1"
# Select CPU PL2/PL4 config
register "cpu_pl2_4_cfg" = "baseline"
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
@ -83,7 +86,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(6),
.icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 1030,
.dc_loadline = 1030,
@ -98,7 +101,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(70),
.icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 180,
.dc_loadline = 180,
@ -113,7 +116,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(31),
.icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
@ -128,7 +131,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(31),
.icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,