From 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 15 Aug 2016 17:58:05 -0700 Subject: [PATCH] gru: Add USB 2.0 PHY tuning for Kevin This patch sets some magic number in magic undocumented registers that are rumored to make USB 2.0 signal integrity better on Kevin. I don't see any difference (unfortunately it doesn't solve the problems with long cables on my board), but I guess it doesn't hurt either way. BRANCH=None BUG=chrome-os-partner:56108,chrome-os-partner:54788 TEST=Booted Kevin with USB connected through Servo. Seems to have roughly the same failure rate as before. Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195 Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/370900 Reviewed-by: Guenter Roeck Reviewed-by: David Schneider --- src/mainboard/google/gru/mainboard.c | 9 +++++++++ src/soc/rockchip/rk3399/include/soc/grf.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 3038d29b19..c9413bdbe3 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -158,6 +158,15 @@ static void configure_display(void) static void setup_usb(void) { + /* A few magic PHY tuning values that improve eye diagram amplitude + * and make it extra sure we get reliable communication in firmware. */ + /* Set max ODT compensation voltage and current tuning reference. */ + write32(&rk3399_grf->usbphy0_ctrl[3], 0x0fff02e3); + write32(&rk3399_grf->usbphy1_ctrl[3], 0x0fff02e3); + /* Set max pre-emphasis level, only on Kevin PHY0. */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) + write32(&rk3399_grf->usbphy0_ctrl[12], 0xffff00a7); + setup_usb_otg0(); setup_usb_otg1(); } diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index d76b827b89..c1fd690e78 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -73,7 +73,7 @@ struct rk3399_grf_regs { u32 reserved11[3]; u32 usbphy0_ctrl[26]; u32 reserved12[6]; - u32 usbphy1[26]; + u32 usbphy1_ctrl[26]; u32 reserved13[0x72f]; u32 soc_con9; u32 reserved14[0x0a];