From 0c3f304d5af1be1d3931e22faf4c47f2387bf4c2 Mon Sep 17 00:00:00 2001 From: Sean Rhodes Date: Tue, 28 Oct 2025 09:28:16 +0000 Subject: [PATCH] mb/starlabs/byte_adl: Enable Wake On Lan Change-Id: I61e6e2b54fb41d610598af08b3f86009a5d539e5 Signed-off-by: Sean Rhodes Reviewed-on: https://review.coreboot.org/c/coreboot/+/89783 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/starlabs/byte_adl/Kconfig | 1 + .../starlabs/byte_adl/variants/mk_ii/devicetree.cb | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig index f3cc349142..d3df0e0c44 100644 --- a/src/mainboard/starlabs/byte_adl/Kconfig +++ b/src/mainboard/starlabs/byte_adl/Kconfig @@ -7,6 +7,7 @@ config BOARD_STARLABS_BYTE_SERIES select DRIVERS_EFI_VARIABLE_STORE select DRIVERS_INTEL_PMC select DRIVERS_OPTION_CFR_ENABLED + select DRIVERS_PCIE_GENERIC select EC_STARLABS_ITE select EC_STARLABS_MERLIN select HAVE_ACPI_RESUME diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 6cb92be551..40635bde30 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -154,6 +154,10 @@ chip soc/intel/alderlake .PcieRpL1Substates = L1_SS_L1_2, }" + chip drivers/pcie/generic + register "wake_gpe" = "GPE0_PME_B0" + device generic 0 on end + end smbios_slot_desc "SlotTypePciExpressGen4x1" "SlotLengthShort" "SlotTypePci" @@ -167,6 +171,10 @@ chip soc/intel/alderlake .pcie_rp_aspm = ASPM_L0S_L1, .PcieRpL1Substates = L1_SS_L1_2, }" + chip drivers/pcie/generic + register "wake_gpe" = "GPE0_PME_B0" + device generic 0 on end + end smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "SlotTypePci"