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skl mainboards/dt: Drop SsicPortEnable setting if disabled

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The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.

Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Felix Singer 2024-06-23 03:56:43 +02:00
commit 0c1daa59b9
17 changed files with 0 additions and 18 deletions
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1
src/mainboard/51nb/x210/devicetree.cb
View file

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[2]" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
View file

@ -41,7 +41,6 @@ chip soc/intel/skylake
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on
register "SsicPortEnable" = "0"
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right
register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE

2
src/mainboard/facebook/monolith/devicetree.cb
View file

@ -197,8 +197,6 @@ chip soc/intel/skylake
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C Port 1 */
}"
register "SsicPortEnable" = "0"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,

1
src/mainboard/google/eve/devicetree.cb
View file

@ -40,7 +40,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View file

@ -71,7 +71,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[1]" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/glados/devicetree.cb
View file

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View file

@ -47,7 +47,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View file

@ -35,7 +35,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View file

@ -43,7 +43,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View file

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View file

@ -40,7 +40,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View file

@ -47,7 +47,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View file

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "SataPortsEnable[0]" = "0"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/libretrend/lt1000/devicetree.cb
View file

@ -47,7 +47,6 @@ chip soc/intel/skylake
register "SataSpeedLimit" = "2"
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/protectli/vault_kbl/devicetree.cb
View file

@ -31,7 +31,6 @@ chip soc/intel/skylake
register "SataSalpSupport" = "0"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/purism/librem_skl/devicetree.cb
View file

@ -49,7 +49,6 @@ chip soc/intel/skylake
register "SataPortsDevSlp[2]" = "0"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View file

@ -30,7 +30,6 @@ chip soc/intel/skylake
}"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "SkipExtGfxScan" = "1"
register "SaGv" = "SaGv_Enabled"