diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 987f1f4865..e482ead8c6 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select ALT_CBFS_LOAD_PAYLOAD
+	select ALWAYS_LOAD_OPROM
 	select BACKUP_DEFAULT_SMM_REGION
 	select CACHE_MRC_BIN
 	select CACHE_MRC_SETTINGS
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 8235b3f3df..eac9ac1ec1 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -472,6 +472,7 @@ static void igd_init(struct device *dev)
 {
 	int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
 	u32 rp1_gfx_freq;
+	extern int oprom_is_loaded;
 
 	/* IGD needs to be Bus Master */
 	u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
@@ -510,6 +511,18 @@ static void igd_init(struct device *dev)
 		igd_cdclk_init_haswell(dev);
 		reg_script_run_on_dev(dev, haswell_late_init_script);
 	}
+
+	if (!oprom_is_loaded) {
+		/*
+		 * Enable DDI-A if the Option ROM did not execute:
+		 *
+		 * bit 0: Display detected (RO)
+		 * bit 4: DDI A supports 4 lanes and DDI E is not used
+		 * bit 7: DDI buffer is idle
+		 */
+		gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
+			  DDI_INIT_DISPLAY_DETECTED);
+	}
 }
 
 static void igd_read_resources(struct device *dev)