From 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 14 May 2014 15:59:37 -0700 Subject: [PATCH] samus: Move SPD handling to separate file The code to find the SPD data for the mainboard based on GPIOs is moved from romstage.c into spd.c. It relies on the updated pei_data structure from broadwell instead of the haswell interface. BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/199920 Reviewed-by: Aaron Durbin --- src/mainboard/google/samus/Makefile.inc | 1 + src/mainboard/google/samus/romstage.c | 30 +---------- src/mainboard/google/samus/spd.c | 69 +++++++++++++++++++++++++ src/mainboard/google/samus/spd.h | 33 ++++++++++++ 4 files changed, 105 insertions(+), 28 deletions(-) create mode 100644 src/mainboard/google/samus/spd.c create mode 100644 src/mainboard/google/samus/spd.h diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc index 87b635da1b..f865b5b05c 100644 --- a/src/mainboard/google/samus/Makefile.inc +++ b/src/mainboard/google/samus/Makefile.inc @@ -25,6 +25,7 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ## DIMM SPD for on-board memory +romstage-y += spd.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 8a879b5c74..3d4d424587 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -70,33 +70,6 @@ const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -/* Copy SPD data for on-board memory */ -static void copy_spd(struct pei_data *peid) -{ - const int gpio_vector[] = {67, 68, 69, -1}; - int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; - - printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); - if (!spd_file) - die("SPD data not found."); - - if (ntohl(spd_file->len) < - ((spd_index + 1) * sizeof(peid->spd_data[0]))) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file->len < sizeof(peid->spd_data[0])) - die("Missing SPD data."); - - memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { @@ -158,9 +131,10 @@ void mainboard_romstage_entry(unsigned long bist) .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, - .copy_spd = copy_spd, }; + mainboard_fill_spd_data(&pei_data); + /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); } diff --git a/src/mainboard/google/samus/spd.c b/src/mainboard/google/samus/spd.c new file mode 100644 index 0000000000..61363f3a16 --- /dev/null +++ b/src/mainboard/google/samus/spd.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "gpio.h" +#include "spd.h" + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + int spd_gpio[3]; + int spd_index; + int spd_file_len; + struct cbfs_file *spd_file; + + spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); + spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); + spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); + + spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; + + printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", + spd_index, + SPD_GPIO_BIT2, spd_gpio[2], + SPD_GPIO_BIT1, spd_gpio[1], + SPD_GPIO_BIT0, spd_gpio[0]); + + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + spd_file_len = ntohl(spd_file->len); + + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Assume same memory in both channels */ + spd_index *= SPD_LEN; + memcpy(pei_data->spd_data[0][0], + ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); + memcpy(pei_data->spd_data[1][0], + ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); +} diff --git a/src/mainboard/google/samus/spd.h b/src/mainboard/google/samus/spd.h new file mode 100644 index 0000000000..0597ac382e --- /dev/null +++ b/src/mainboard/google/samus/spd.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +/* Samus board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 67 +#define SPD_GPIO_BIT1 68 +#define SPD_GPIO_BIT2 69 + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif