UPSTREAM: AGESA: BIST is already preserved

Officialy we enter with BIST in %eax, but %ebp is old backup register.
Note that post_code() destroys %al.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ic3f210d22cb1efae868ab29911dda63449475184
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1779d534e5
Original-Change-Id: I77b9a80aac11ae301fdda71c2a20803d7a5fb888
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/18625
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/471449

src/cpu/amd/agesa/cache_as_ram.inc

@@ -28,7 +28,6 @@
 
 /*
  * XMM map:
- *   xmm0: BIST
  */
 
 .code32
@@ -36,6 +35,9 @@
 
 cache_as_ram_setup:
 
+  /* Preserve BIST. */
+  movl %eax, %ebp
+
   post_code(0xa0)
 
   /* enable SSE2 128bit instructions */
@@ -45,11 +47,9 @@ cache_as_ram_setup:
   orl $(3<<9), %eax
   movl %eax, %cr4
 
-  /* Save the BIST result */
-  cvtsi2sd  %ebp, %xmm0
-
   post_code(0xa1)
 
+  /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */
   AMD_ENABLE_STACK
 
   /* Align the stack. */
@@ -100,16 +100,15 @@ cache_as_ram_setup:
 
 #endif
 
-  call early_all_cores
+  /* Calling conventions preserve BIST in %ebp. */
 
-  /* Restore the BIST result */
-  cvtsd2si  %xmm0, %edx
+  call early_all_cores
 
   /* Must maintain 16-byte stack alignment here. */
   pushl $0x0
   pushl $0x0
   pushl $0x0
-  pushl %edx  /* bist */
+  pushl %ebp
   call  romstage_main
 
   /* Should never see this postcode */