Changes to allow Via/Epia code to be compiled after recent code changes.
New Files :- src/cpu/via/model_centaur/Config.lb src/cpu/via/model_centaur/model_centaur_init.c Updated Files :- src/arch/i386/include/arch/smp/mpspec.h - make write_smp_table a define for non smp systems src/cpu/x86/lapic/lapic_cpu_init.c - change possible typo src/mainboard/via/epia/Config.lb src/mainboard/via/epia/Options.lb src/mainboard/via/epia/auto.c src/mainboard/via/epia/chip.h src/mainboard/via/epia/failover.c - updated after recent code changes src/northbridge/via/vt8601/chip.h src/northbridge/via/vt8601/northbridge.c src/northbridge/via/vt8601/raminit.c - corrections after recent code changes to allow compiling src/southbridge/via/vt8231/chip.h src/southbridge/via/vt8231/vt8231.c - initial pass to allow compiling after recent code changes. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Mark Wilkinson
parent
97035448f3
commit
0afcba7a3d
15 changed files with 162 additions and 103 deletions
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@ -14,9 +14,8 @@ end
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default CONFIG_ROM_STREAM = 1
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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@ -45,6 +44,7 @@ arch i386 end
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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##
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@ -128,59 +128,63 @@ dir /pc80
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config chip.h
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chip northbridge/via/vt8601
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# pci 0:0.0
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# pci 0:1.0
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chip southbridge/via/vt8231
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# pci 0:11.0
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# pci 0:11.1
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# pci 0:11.2
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# pci 0:11.3
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# pci 0:11.4
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# pci 0:11.5
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# pci 0:11.6
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# pci 0:12.0
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register "enable_usb" = "0"
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register "enable_native_ide" = "0"
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register "enable_com_ports" = "1"
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register "enable_keyboard" = "0"
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register "enable_nvram" = "1"
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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register "com1" = "{1}"
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# register "com1" = "{1, 0, 0x3f8, 4}"
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# register "lpt" = "{1}"
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end
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end
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device pci_domain 0 on
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device pci 0.0 on
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chip southbridge/via/vt8231
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register "enable_usb" = "0"
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register "enable_native_ide" = "0"
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register "enable_com_ports" = "1"
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register "enable_keyboard" = "0"
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register "enable_nvram" = "1"
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device pci 11.0 on # Southbridge
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device pci 11.1 on end # Ide
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device pci 11.2 off end # Usb
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device pci 11.3 off end # Usb
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device pci 11.4 off end # ACPI
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device pci 11.5 off end # Audio
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device pci 11.6 on # Com
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GAME_MIDI_GIPO1
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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register "com1" = "{1}"
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end
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end
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device pci 12.0 on end # Ethernet
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end
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end
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end
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end
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chip cpu/via/model_centaur
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end
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end
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##
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@ -188,3 +192,4 @@ end
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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@ -68,6 +68,7 @@ default HAVE_OPTION_TABLE=1
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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default ROM_IMAGE_SIZE = 65536
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default FALLBACK_SIZE = 131072
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##
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## Use a small 8K stack
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@ -87,4 +88,7 @@ default USE_OPTION_TABLE = 0
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default _RAMBASE = 0x00004000
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default CONFIG_ROM_STREAM = 1
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end
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@ -2,7 +2,7 @@
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <cpu/x86/lapic.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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@ -11,7 +11,7 @@
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/via/vt8601/raminit.h"
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#include "cpu/p6/earlymtrr.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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/*
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*/
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@ -23,7 +23,7 @@ void udelay(int usecs)
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}
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "debug.c"
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#include "southbridge/via/vt8231/vt8231_early_smbus.c"
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@ -96,8 +96,6 @@ static void enable_shadow_ram(void)
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static void main(void)
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{
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unsigned long x;
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/* init_timer();*/
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outb(5, 0x80);
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enable_vt8231_serial();
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@ -1,4 +1,4 @@
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extern struct chip_operations mainboard_via_epia_control;
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extern struct chip_operations mainboard_via_epia_ops;
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struct mainboard_via_epia_config {
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int nothing;
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@ -5,7 +5,7 @@
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#include <arch/io.h>
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#include "arch/romcc_io.h"
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#include "pc80/mc146818rtc_early.c"
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#include "cpu/p6/boot_cpu.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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static void main(void)
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{
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@ -7,8 +7,8 @@
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#include <arch/io.h>
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#include "chip.h"
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static int
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mainboard_scan_bus(device_t root, int maxbus)
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static unsigned int
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mainboard_scan_bus(device_t root, unsigned int maxbus)
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{
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int retval;
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printk_spew("%s: root %p maxbus %d\n", __FUNCTION__, root, maxbus);
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@ -31,7 +31,7 @@ static void enable_dev(device_t dev)
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dev->ops = &mainboard_operations;
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}
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struct chip_operations mainboard_via_epia_control = {
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struct chip_operations mainboard_via_epia_ops = {
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.enable_dev = enable_dev,
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.name = "VIA EPIA mainboard ",
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};
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