From 0ac29ad3ce7340c462d9580aafc6f965a3014137 Mon Sep 17 00:00:00 2001
From: Maximilian Brune <maximilian.brune@9elements.com>
Date: Thu, 12 Sep 2024 17:36:13 -0700
Subject: [PATCH] device/dram/ddr5: Add 7500 MT/s support

Before I got the following error:
[ERROR]  DDR5 speed of 3750 MHz is out of range

tested: glinda based mainboard

Change-Id: I141f63c4fc505a9e16eed132a9a550441f4ad68d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86543
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Naresh Solanki <naresh.solanki@9elements.com>
---
 src/device/dram/ddr5.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/device/dram/ddr5.c b/src/device/dram/ddr5.c
index b546abf4d4..90b67f857b 100644
--- a/src/device/dram/ddr5.c
+++ b/src/device/dram/ddr5.c
@@ -21,6 +21,7 @@ enum ddr5_speed_grade {
 	DDR5_5500,
 	DDR5_6000,
 	DDR5_6400,
+	DDR5_7500,
 };
 
 struct ddr5_speed_attr {
@@ -108,6 +109,11 @@ static const struct ddr5_speed_attr ddr5_speeds[] = {
 		.max_clock_mhz = 3200,
 		.reported_mts = 6400
 	},
+	[DDR5_7500] = {
+		.min_clock_mhz = 3201,
+		.max_clock_mhz = 3750,
+		.reported_mts = 7500
+	},
 };
 
 /**