From 0a7c3ed514d2ba41e15df846b10717dcec13adab Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Mon, 2 Dec 2024 16:12:17 +0800 Subject: [PATCH] soc/mediatek/mt8195: Fix SCP register address The parentheses are missing in the mtk_scp macro definition. The only usage is SET32_BITFIELDS(&mtk_scp->scp_clk_on_ctrl, SCP_CLK_ON_CTRL, 1); I guess that bit is already set by default, so there's no ULPOSC clock issue found so far. BUG=none TEST=none BRANCH=cherry Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/85436 Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin --- src/soc/mediatek/mt8195/include/soc/pmif.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8195/include/soc/pmif.h b/src/soc/mediatek/mt8195/include/soc/pmif.h index cec23d7ca1..530b31ea62 100644 --- a/src/soc/mediatek/mt8195/include/soc/pmif.h +++ b/src/soc/mediatek/mt8195/include/soc/pmif.h @@ -134,7 +134,7 @@ struct mtk_scp_regs { check_member(mtk_scp_regs, scp_clk_on_ctrl, 0x6C); -#define mtk_scp ((struct mtk_scp_regs *)SCP_CFG_BASE + 0x21000) +#define mtk_scp ((struct mtk_scp_regs *)(SCP_CFG_BASE + 0x21000)) enum { PMIF_TARGET_FREQ_MHZ = 248,