From 0a6142dfbe4b81442e4e307ccd087759aae5a4a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 16 Sep 2025 08:22:41 +0200 Subject: [PATCH] soc/amd/turin_poc: Add SPI TPM SoC-specific initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the SoC hook to initialize SPI TPM decoding. Without the additional programming an attempt to talk to SPI TPM hangs the platform when the TPM_MEASURED_BOOT_INIT_BOOTBLOCK is set. If TPM is initialized in ramstage, the OpenSIL programs the SPI TPM decoding properly and the issue is not observed. TEST=Select TPM_MEASURED_BOOT_INIT_BOOTBLOCK and enable TPM_MEASURED_BOOT on Gigabyte MZ33-AR1, and observe the platform does not hang in bootblock. Change-Id: I2e6c0aad31fd0335e0d16111ed4894a12d2ba497 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/89192 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- src/soc/amd/turin_poc/Makefile.mk | 3 +++ src/soc/amd/turin_poc/lpc.c | 11 +++++++++++ 2 files changed, 14 insertions(+) create mode 100644 src/soc/amd/turin_poc/lpc.c diff --git a/src/soc/amd/turin_poc/Makefile.mk b/src/soc/amd/turin_poc/Makefile.mk index 68144574c2..5cbcbea405 100644 --- a/src/soc/amd/turin_poc/Makefile.mk +++ b/src/soc/amd/turin_poc/Makefile.mk @@ -8,6 +8,9 @@ all-y += i2c.c all-y += i3c.c all-y += uart.c +all-y += lpc.c +smm-y += lpc.c + bootblock-y += early_fch.c bootblock-y += aoac.c diff --git a/src/soc/amd/turin_poc/lpc.c b/src/soc/amd/turin_poc/lpc.c new file mode 100644 index 0000000000..23a32f5de3 --- /dev/null +++ b/src/soc/amd/turin_poc/lpc.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void soc_lpc_tpm_decode_spi(void) +{ + /* SoC-specific SPI TPM setting */ + pci_or_config32(SOC_LPC_DEV, 0xdc, 1); +}