From 09d689561a68c5f3023953e07632411e85ed5172 Mon Sep 17 00:00:00 2001 From: Payne Lin Date: Wed, 11 Mar 2026 15:43:15 +0800 Subject: [PATCH] soc/mediatek/common: dsi: Fix CPHY hfp_byte error check In CPHY mode, mtk_dsi_cphy_vdo_timing previously packed multiple values into hfp_byte: - Bits [7:0]: actual HFP byte count - Bits [30:16]: hs_vb_ps_wc - Bit 31: HFP_HS_EN flag The previous error check treated the entire compound value as the HFP byte count, resulting in false error messages like: "Calculated hfp_byte -1850408952 and hbp_byte 4 are too small" This patch refactors mtk_dsi_cphy_vdo_timing to return hfp_byte and the upper bits (hfp_wc_upper) separately: - hfp_byte now consistently represents the actual HFP byte count for both CPHY and DPHY modes - hfp_wc_upper contains hs_vb_ps_wc and HFP_HS_EN for CPHY (0 for DPHY) - The values are combined when writing to dsi_hfp_wc register This approach: - Eliminates the need for mask operations in the caller - Simplifies hfp/hbp validation and adjustment logic - Makes hfp_byte semantically consistent across CPHY/DPHY BUG=b:489932059 TEST=Boot and verify display output on MT8189 CPHY panel BRANCH=skywalker Signed-off-by: Payne Lin Change-Id: I46229c35f978a88276f4ae2a4582b2ea4164c1db Signed-off-by: Cindy Lu Reviewed-on: https://review.coreboot.org/c/coreboot/+/91683 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin --- src/soc/mediatek/common/dsi_common.c | 10 +++++++--- src/soc/mediatek/common/include/soc/dsi_common.h | 3 ++- src/soc/mediatek/common/mtk_mipi_cphy.c | 7 +++++-- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/soc/mediatek/common/dsi_common.c b/src/soc/mediatek/common/dsi_common.c index 04dc0a85c3..4071cee41a 100644 --- a/src/soc/mediatek/common/dsi_common.c +++ b/src/soc/mediatek/common/dsi_common.c @@ -278,6 +278,8 @@ static void mtk_dsi_config_vdo_timing(struct dsi_regs *const dsi_reg, u32 mode_f u32 hbp_offset; bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY); bool is_dsc_enabled = !!(mode_flags & MIPI_DSI_DSC_MODE); + bool cphy_mode; + u32 hfp_wc_upper = 0; int channels = !!(mode_flags & MIPI_DSI_DUAL_CHANNEL) ? 2 : 1; int dsc_ratio = is_dsc_enabled ? COMPRESSION_RATIO : UNCOMPRESSED_RATIO; @@ -301,9 +303,11 @@ static void mtk_dsi_config_vdo_timing(struct dsi_regs *const dsi_reg, u32 mode_f hfp_byte = hfp * bytes_per_pixel; - if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) + cphy_mode = CONFIG(MEDIATEK_DSI_CPHY) && is_cphy; + + if (cphy_mode) mtk_dsi_cphy_vdo_timing(lanes, edid, phy_timing, bytes_per_pixel, hbp, hfp, - &hbp_byte, &hfp_byte, &hsync_active_byte); + &hbp_byte, &hfp_byte, &hsync_active_byte, &hfp_wc_upper); else mtk_dsi_dphy_vdo_timing(mode_flags, lanes, edid, phy_timing, bytes_per_pixel, hbp, hfp, &hbp_byte, &hfp_byte, &hsync_active_byte); @@ -325,7 +329,7 @@ static void mtk_dsi_config_vdo_timing(struct dsi_regs *const dsi_reg, u32 mode_f write32(&dsi_reg->dsi_hsa_wc, hsync_active_byte); write32(&dsi_reg->dsi_hbp_wc, hbp_byte); - write32(&dsi_reg->dsi_hfp_wc, hfp_byte); + write32(&dsi_reg->dsi_hfp_wc, hfp_byte | hfp_wc_upper); if (is_dsc_enabled) packet_fmt = COMPRESSED_PIXEL_STREAM_V2; diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 62bff790a9..f9ebd58866 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -179,7 +179,8 @@ void mtk_dsi_cphy_timing(struct dsi_regs *dsi_reg, u32 data_rate, void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid, const struct mtk_phy_timing *phy_timing, const u32 bytes_per_pixel, const u32 hbp, const u32 hfp, - s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte); + s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte, + u32 *hfp_wc_upper); void mtk_dsi_cphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg); void mtk_dsi_dphy_disable_ck_mode(struct mipi_tx_regs *mipi_tx_reg); void mtk_dsi_dphy_timing_calculation(u32 data_rate_mhz, struct mtk_phy_timing *timing); diff --git a/src/soc/mediatek/common/mtk_mipi_cphy.c b/src/soc/mediatek/common/mtk_mipi_cphy.c index ecf7915f67..1bf289abb9 100644 --- a/src/soc/mediatek/common/mtk_mipi_cphy.c +++ b/src/soc/mediatek/common/mtk_mipi_cphy.c @@ -91,7 +91,8 @@ void mtk_dsi_cphy_vdo_timing(const u32 lanes, const u32 hfp, s32 *hbp_byte, s32 *hfp_byte, - u32 *hsync_active_byte) + u32 *hsync_active_byte, + u32 *hfp_wc_upper) { s32 active_byte, phy_cycle, phy_trail, tmp; u32 hs_vb_ps_wc, ps_wc, data_phy_cycles; @@ -106,8 +107,10 @@ void mtk_dsi_cphy_vdo_timing(const u32 lanes, phy_trail = 2 * (phy_timing->da_hs_trail + 1) * lanes - 6 * lanes - 14; tmp = hfp * bytes_per_pixel - phy_cycle; *hfp_byte = MIN(MAX(8, tmp), phy_trail); + + /* Return upper bits separately for CPHY HFP_WC register */ ps_wc = edid->mode.ha * bytes_per_pixel; hs_vb_ps_wc = ps_wc - (phy_timing->lpx + phy_timing->da_hs_exit + phy_timing->da_hs_prepare + phy_timing->da_hs_zero + 2) * lanes; - *hfp_byte |= hs_vb_ps_wc << 16 | HFP_HS_EN; + *hfp_wc_upper = hs_vb_ps_wc << 16 | HFP_HS_EN; }