From 098a5cf16e5a972216833fedd57d594185668b15 Mon Sep 17 00:00:00 2001 From: Sowmya V Date: Tue, 17 Feb 2026 17:06:57 +0530 Subject: [PATCH] mb/google/ocelot: Configure CDCLK frequency for display Configure the Core Display Clock (CDCLK) frequency selection by setting the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the ocelot baseboard devicetree. This ensures the display engine operates at the required frequency for the panel to meet the hardware configuration. TEST=Build and boot ocelot, verify display initialization. Change-Id: Ic2f8fccc4391febd342f8f140014c5f3e09472c4 Signed-off-by: Sowmya V Reviewed-on: https://review.coreboot.org/c/coreboot/+/91312 Reviewed-by: Avi Uday Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- .../google/ocelot/variants/baseboard/ocelot/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb index 23b276e15a..b53380c2ee 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb @@ -95,6 +95,7 @@ chip soc/intel/pantherlake register "pch_hda_idisp_codec_enable" = "true" register "disable_progress_bar" = "true" + register "vga_cd_clk_freq_sel" = "CD_CLK_461MHZ" device domain 0 on device ref dtt on end