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UPSTREAM: intel/amenia: Add GPIO changes to assert SLP_S0/Reset signal

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PMIC/PMU: Set the iosstates for PMIC to assert the reset
signal, PMU to assert SLP_S0 signal.

BUG=None
BRANCH=None
TEST=None

Change-Id: Ieae0e1a35ddde020f1bceedc26fa6d4d5700f861
Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/15777
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/367367
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Shankar, Vaibhav 2016-07-18 12:07:34 -07:00 • committed by chrome-bot
commit 097712c8f2
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/intel/amenia/gpio.h
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@ -120,7 +120,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */
PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */
PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */
PAD_CFG_NF(PMU_SLP_S0_B, NONE, DEEP, NF1), /* PMU_SLP_S0_N */
PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */
PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */
PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */
PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */
@ -164,7 +164,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(PMC_SPI_CLK, DN_20K), /* PMC_SPI_CLK */
/* PMIC */
PAD_NC(PMIC_PWRGOOD, NONE), /* PMIC_PWRGOOD */
PAD_NC(PMIC_RESET_B, NONE), /* PMIC_RESET_B */
PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */
PAD_NC(GPIO_213, NONE), /* PMIC_SDWN_B */
PAD_NC(GPIO_214, DN_20K), /* PMIC_BCUDISW2 */
PAD_NC(GPIO_215, DN_20K), /* PMIC_BCUDISCRIT */