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UPSTREAM: mb/gigabyte/ga-g41m-es2l: Tie in configuration for SuperIO EC

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BUG=None
BRANCH=None
TEST=None

Signed-off-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17602
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Ifba821a7e355a0d6689f21c7f307e3901903a3fd
Reviewed-on: https://chromium-review.googlesource.com/415091
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Damien Zammit 2016-11-25 22:10:19 +11:00 • committed by chrome-bot
commit 0926a64d01
1 changed files with 25 additions and 0 deletions
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src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
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@ -82,6 +82,31 @@ chip northbridge/intel/x4x # Northbridge
device pci 1f.0 on # ISA bridge
subsystemid 0x1458 0x5001
chip superio/ite/it8718f # Super I/O
register "TMPIN1" = "THERMAL_RESISTOR"
register "TMPIN2" = "THERMAL_RESISTOR"
register "TMPIN3" = "THERMAL_DIODE"
register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0"
register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
register "FAN1.smart.tmpin" = "3"
register "FAN1.smart.tmp_off" = "25"
register "FAN1.smart.tmp_start" = "30"
register "FAN1.smart.tmp_full" = "65"
register "FAN1.smart.tmp_delta" = "3"
register "FAN1.smart.smoothing" = "1"
register "FAN1.smart.pwm_start" = "0"
register "FAN1.smart.slope" = "10"
register "FAN2.mode" = "FAN_SMART_AUTOMATIC"
register "FAN2.smart.tmpin" = "3"
register "FAN2.smart.tmp_off" = "25"
register "FAN2.smart.tmp_start" = "30"
register "FAN2.smart.tmp_full" = "65"
register "FAN2.smart.tmp_delta" = "3"
register "FAN2.smart.smoothing" = "1"
register "FAN2.smart.pwm_start" = "0"
register "FAN2.smart.slope" = "10"
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6