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Architecture changes. This gets us through stage 2.

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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com> 
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@76 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Stefan Reinauer 2007-02-22 21:39:25 +00:00
commit 0850d0cad8
3 changed files with 28 additions and 18 deletions
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12
arch/x86/Makefile
View file

@ -52,8 +52,9 @@ initram:
# This needs to be compressed with the default compressor
#
linuxbios_ram: $(obj)/statictree.o
$(obj)/linuxbios.stage2: $(obj)/statictree.o
$(Q)echo "building linuxbios_ram"
touch $(obj)/linuxbios.stage2
#
# The payload as we love it. Get it from somewhere.
@ -70,13 +71,14 @@ payload:
# build the lar archive
#
$(obj)/linuxbios.lar: $(obj)/util/lar/lar lzma linuxbios.initram linuxbios_ram payload
$(obj)/linuxbios.lar: $(obj)/util/lar/lar lzma $(obj)/linuxbios.initram $(obj)/linuxbios.stage2 payload
$(Q)echo "Building LinuxBIOS archive..."
$(Q)rm -rf $(obj)/lar.tmp
$(Q)mkdir $(obj)/lar.tmp
$(Q)mkdir $(obj)/lar.tmp/normal
$(Q)cp $(obj)/linuxbios.initram $(obj)/lar.tmp/normal/initram
$(Q)cd $(obj)/lar.tmp && ../util/lar/lar c ../linuxbios.lar.pre normal/initram
$(Q)cp $(obj)/linuxbios.stage2 $(obj)/lar.tmp/normal/stage2
$(Q)cd $(obj)/lar.tmp && ../util/lar/lar c ../linuxbios.lar.pre normal/initram normal/stage2
# TODO: dynamically pad the lar archive. bs is image size - bootblock size (8k)
$(Q)dd if=$(obj)/linuxbios.lar.pre of=$(obj)/linuxbios.lar bs=253952 count=1 conv=sync
@ -103,10 +105,10 @@ $(obj)/stage0.init:
@$(CC) $(INITCFLAGS) -c $(src)/console/vtxprintf.c -o $(obj)/vtxprintf.o
@$(CC) $(INITCFLAGS) -c $(src)/lib/uart8250.c -o $(obj)/uart8250.o
# other lib parts
@$(CC) $(INITCFLAGS) -c $(src)/lib/memcpy.c -o $(obj)/memcpy.o
@$(CC) $(INITCFLAGS) -c $(src)/lib/mem.c -o $(obj)/mem.o
@cd $(obj); $(CC) -m32 -nostdlib -static -T $(src)/arch/x86/ldscript.ld cachemain.o console.o uart8250.o \
serial.o vtxprintf.o lar.o memcpy.o stage0_i586.o -o stage0.o
serial.o vtxprintf.o lar.o mem.o stage0_i586.o -o stage0.o
@objcopy -O binary $(obj)/stage0.o $(obj)/stage0.init.pre
# Pad boot block to 0x2000 - 0x100

30
arch/x86/cachemain.c
View file

@ -30,7 +30,7 @@ void console_init(void);
void die(const char *msg);
int find_file(struct mem_file *archive, char *filename, struct mem_file *result);
static void post_code(u8 value)
void post_code(u8 value)
{
outb(value, 0x80);
}
@ -90,25 +90,33 @@ void stage1_main(u32 bist)
// but NOT IN THE CODE.
archive.len=LINUXBIOS_ROMSIZE_KB*1024;
archive.start=(void *)(0UL-archive.len);
archive.start=(void *)(0UL-archive.len);
/* This won't work; the for loop in lib/lar.c will always
* fail as adding len to start will be 0.
* shave off 0x1000 since we know that is the boot block
*/
archive.len-=0x1000;
printk(BIOS_INFO, "Start search at 0x%x, size %d\n", archive.start, archive.len);
// FIXME check integrity
// fixme: choose an initram image (normal/fallback)
// find first initram
ret=find_file(&archive, "normal/initram", &result);
if(!ret) {
void (*initram)(void);
initram=(result.start);
printk(BIOS_INFO, "Jumping to RAM init code at 0x%08x\n",
result.start);
initram();
ret = run_file(&archive, "normal/initram", (void *)(512*1024)); //CONFIG_CARBASE;
}
if (ret)
die("Failed ram init code\n");
die ("FATAL: No initram module found\n");
printk(BIOS_INFO, "Done ram init code\n");
ret = run_file(&archive, "normal/stage2", (void *)0x1000);
if (ret)
die("Failed stage2 code\n");
printk(BIOS_INFO, "Done stage2 code\n");
die ("FATAL: This is as far as it goes\n");
}

4
arch/x86/config.h
View file

@ -20,9 +20,9 @@
/* This config file is a place holder and will be created dynamically soon */
#define LINUXBIOS_VERSION "3.0.0-wth"
#define LINUXBIOS_VERSION "3.0.0"
#define LINUXBIOS_BUILD "Fri Jan 19 15:24:28 CET 2007"
#define LINUXBIOS_ROMSIZE_KB 512
#define LINUXBIOS_ROMSIZE_KB 256
#define TTYS0_BASE 0x3f8