AGESA vendorcode: Build a common amdlib

Having CFLAGS with -Os disables -falign-function, for
unlucky builds this may delay entry to ramstage by 600ms.
Build the low-level IO functions aligned with -O2 instead.

Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/amd/agesa/family15/fixme.c

@@ -17,6 +17,35 @@
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include "amdlib.h"
 
+UINT64
+MsrRead (
+  IN       UINT32 MsrAddress
+  );
+
+VOID
+MsrWrite (
+  IN       UINT32 MsrAddress,
+  IN			 UINT64 Value
+  );
+
+
+UINT64
+MsrRead (
+  IN       UINT32 MsrAddress
+  )
+{
+  return __readmsr (MsrAddress);
+}
+
+VOID
+MsrWrite (
+  IN       UINT32 MsrAddress,
+  IN			 UINT64 Value
+  )
+{
+  __writemsr (MsrAddress, Value);
+}
+
 #if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
 void amd_initcpuio(void)
 {