From 08076240bdc10894b8e790e4b52adf4344fff261 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Mon, 3 Mar 2025 11:44:53 +0530 Subject: [PATCH] mb/google/brya: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. BUG=b:391612392 TEST=Run suspend_stress_test on brya device and verify that the device suspends to S0ix. Change-Id: Ifc85b85ef57216dc394f9a2e1b25bb7154da658f Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/86685 Reviewed-by: Eric Lai Reviewed-by: Subrata Banik Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- .../google/brya/variants/baseboard/brya/devicetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 6160ebf084..3a748ea0f1 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -192,6 +192,13 @@ chip soc/intel/alderlake .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "1" + device generic 0 on end + end end #PCIE9-12 SSD device ref uart0 on end device ref gspi1 on end