epia-m initial checkin
This commit is contained in:
Andrew Ip
parent
28e6775d27
commit
07abf26642
16 changed files with 1102 additions and 0 deletions
5
src/mainboard/via/epia-m/README
Normal file
5
src/mainboard/via/epia-m/README
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@ -0,0 +1,5 @@
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To enable flash write,
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$ setpci -s 0:11.0 40.b=54
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-Andrew
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27
src/mainboard/via/epia-m/STATUS
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27
src/mainboard/via/epia-m/STATUS
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@ -0,0 +1,27 @@
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# These are keyword-value pairs.
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# a : separates the keyword from the value
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# the value is arbitrary text delimited by newline.
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# continuation, if needed, will be via the \ at the end of a line
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# comments are indicated by a '#' as the first character.
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# the keywords are case-INSENSITIVE
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owner: Andrew Ip
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email: aip@cwlinux.com
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#status: One of unsupported, unstable, stable
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status: unstable
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explanation: slow performance
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flash-types: SST 39SF020A
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payload-types: etherboot, memtest
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# e.g. linux, plan 9, wince, etc.
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OS-types: linux
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# e.g. "Plan 9 interrupts don't work on this chipset"
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OS-issues:
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console-types: serial
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# vga is unsupported, unstable, or stable
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vga: unsupported
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# Last-known-good follows the internationl date standard: day/month/year
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last-known-good: 0/0/0000
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Comments:
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Links:
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Mainboard-revision:
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# What other mainboards are like this one? List them here.
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AKA:
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8
src/mainboard/via/epia-m/do_dumpdev.inc
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8
src/mainboard/via/epia-m/do_dumpdev.inc
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@ -0,0 +1,8 @@
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movl $0x0, %ecx
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CALLSP(dumpdev)
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movl $CONFIG_ADDR(0,0x88,0), %ecx
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CALLSP(dumpdev)
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movl $CONFIG_ADDR(0,0x89,0), %ecx
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CALLSP(dumpdev)
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1
src/mainboard/via/epia-m/do_dumpnorth.inc
Normal file
1
src/mainboard/via/epia-m/do_dumpnorth.inc
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@ -0,0 +1 @@
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CALLSP(dumpnorth)
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5
src/mainboard/via/epia-m/do_ramtest.inc
Normal file
5
src/mainboard/via/epia-m/do_ramtest.inc
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@ -0,0 +1,5 @@
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mov $0x00000000, %eax
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mov $0x0009ffff, %ebx
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mov $16, %ecx
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CALLSP(ramtest)
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65
src/mainboard/via/epia-m/dumpdev.inc
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65
src/mainboard/via/epia-m/dumpdev.inc
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@ -0,0 +1,65 @@
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/* Dump the first 64 longs for devfn 0, bus 0
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* i.e. the north bridge.
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*/
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#define CS_WRITE_BYTE(addr, byte) \
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movl $addr, %eax ; \
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movl $byte, %edx ; \
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PCI_WRITE_CONFIG_BYTE
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#define CS_WRITE_WORD(addr, word) \
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movl $addr, %eax ; \
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movl $word, %ecx ; \
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PCI_WRITE_CONFIG_WORD
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#define CS_WRITE_LONG(addr, dword) \
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movl $addr, %eax ; \
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movl $dword, %ecx ; \
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PCI_WRITE_CONFIG_DWORD
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#define DEVFN(device, function) (((device) << 3) + (function))
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#ifndef CONFIG_ADDR
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#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
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#endif
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jmp dumpdev_skip
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.section ".rom.data"
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dd_banner: .string "dump device: "
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dd_ret: .string "\r\n"
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dd_done: .string "Done.\r\n"
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dd_before: .string "Before setting values: \r\n"
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dd_after: .string "After setting values: \r\n"
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.previous
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# expects device devfn in %ecx
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dumpdev:
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mov %esp, %ebp
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CONSOLE_INFO_TX_STRING($dd_banner)
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CONSOLE_INFO_TX_HEX32(%ecx)
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CONSOLE_INFO_TX_STRING($dd_ret)
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# xorl %ecx, %ecx
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1:
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CONSOLE_INFO_TX_HEX8(%cl)
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CONSOLE_INFO_TX_CHAR($':')
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CONSOLE_INFO_TX_CHAR($' ')
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2:
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movl %ecx, %eax
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PCI_READ_CONFIG_BYTE
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CONSOLE_INFO_TX_HEX8(%al)
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CONSOLE_INFO_TX_CHAR($' ')
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incl %ecx
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testb $0xf, %cl
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jnz 2b
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CONSOLE_INFO_TX_CHAR($'\r')
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CONSOLE_INFO_TX_CHAR($'\n')
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cmpb $0, %cl
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jne 1b
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CONSOLE_INFO_TX_STRING($dd_done)
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mov %ebp, %esp
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RETSP
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dumpdev_skip:
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31
src/mainboard/via/epia-m/example.config
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31
src/mainboard/via/epia-m/example.config
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#
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# LinuxBIOS config file for: VIA epia mini-itx
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#
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target /opt/cwlinux/buildrom/epia
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# via epia
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mainboard via/epia
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE=1
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option TTYS0_BAUD=115200
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option DEFAULT_CONSOLE_LOGLEVEL=9
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option DEBUG=1
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# Use 256KB Standard Flash as Normal BIOS
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option RAMTEST=1
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option USE_GENERIC_ROM=1
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option STD_FLASH=1
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#option ZKERNEL_START=0xfffc0000
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option ROM_SIZE=262144
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# payload size = 192KB
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option PAYLOAD_SIZE=196608
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# use ELF Loader to load Etherboot
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option USE_ELF_BOOT=1
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# Use Etherboot as our payload
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payload /opt/cwlinux/etherboot/src/bin32/via-rhine.ebi
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46
src/mainboard/via/epia-m/irq_tables.c
Normal file
46
src/mainboard/via/epia-m/irq_tables.c
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@ -0,0 +1,46 @@
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
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Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*5, /* there can be total 5 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0, /* Where the interrupt router lies (dev) */
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0x1c20, /* IRQs devoted exclusively to PCI usage */
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0, /* Vendor */
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0, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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#if 0
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0x58, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
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{0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0},
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{0,0x50, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x3, 0},
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{0,0x68, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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{0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0},
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{0x50,0, {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}
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}
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#else
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0xac, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* ethernet */
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{0,0x90, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
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/* usb */
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{0,0x80, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
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/* pci */
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{0,0xa0, {{0x1, 0xdeb8}, {0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}}, 0x3, 0},
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/* audio */
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{0,0x8d, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x0, 0},
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/* 1394 */
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{0,0x68, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}
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}
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#endif
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};
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95
src/mainboard/via/epia-m/mainboard.c
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95
src/mainboard/via/epia-m/mainboard.c
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#include <printk.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <cpu/p5/io.h>
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#include <types.h>
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//static const unsigned char usbIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char usbIrqs[4] = { 11, 12, 10, 5 };
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static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
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//static const unsigned char slotIrqs[4] = { 10, 12, 5, 11 };
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static const unsigned char slotIrqs[4] = { 12, 10, 5, 11 };
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static const unsigned char firewireIrqs[4] = { 12, 10, 5, 11 };
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/*
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Our IDSEL mappings are as follows
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PCI slot is AD31 (device 15) (00:14.0)
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Southbridge is AD28 (device 12) (00:11.0)
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*/
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static void pci_routing_fixup(void)
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{
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struct pci_dev *dev;
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dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x3177, 0);
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if (dev != NULL) {
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/*
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* initialize PCI interupts - these assignments depend
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* on the PCB routing of PINTA-D
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*
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* PINTA = IRQ11
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* PINTB = IRQ12
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* PINTC = IRQ10
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* PINTD = IRQ5
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*/
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pci_write_config_byte(dev, 0x55, 0xb0);
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pci_write_config_byte(dev, 0x56, 0xac);
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pci_write_config_byte(dev, 0x57, 0x50);
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}
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#if 1
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// firewire built into southbridge
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printk_info("setting firewire\n");
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pci_assign_irqs(0, 0x0d, firewireIrqs);
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// Standard usb components
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printk_info("setting usb\n");
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pci_assign_irqs(0, 0x10, usbIrqs);
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// Ethernet built into southbridge
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printk_info("setting ethernet\n");
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pci_assign_irqs(0, 0x12, enetIrqs);
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// PCI slot
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printk_info("setting pci slot\n");
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pci_assign_irqs(0, 0x14, slotIrqs);
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#endif
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printk_debug("4d0: 0x%02x\n", inb(0x4d0));
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printk_debug("4d1: 0x%02x\n", inb(0x4d1));
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#if 0
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outb(0, 0x4d0);
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outb(0, 0x4d1);
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#endif
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printk_debug("4d0: 0x%02x\n", inb(0x4d0));
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printk_debug("4d1: 0x%02x\n", inb(0x4d1));
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}
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void
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mainboard_fixup()
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{
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printk_info("Mainboard fixup\n");
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northbridge_fixup();
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southbridge_fixup();
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}
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void
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final_southbridge_fixup()
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{
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printk_info("Southbridge fixup\n");
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nvram_on();
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// keyboard_on();
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pci_routing_fixup();
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}
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void
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final_mainboard_fixup()
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{
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printk_info("Final mainboard fixup\n");
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final_southbridge_fixup();
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}
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1
src/northbridge/via/vt8623/Config
Normal file
1
src/northbridge/via/vt8623/Config
Normal file
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object northbridge.o
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106
src/northbridge/via/vt8623/northbridge.c
Normal file
106
src/northbridge/via/vt8623/northbridge.c
Normal file
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#include <mem.h>
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#include <part/sizeram.h>
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#include <printk.h>
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#include <pci.h>
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#include <pciconf.h>
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static unsigned long __sizeram(void)
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{
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unsigned long totalmem;
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unsigned char bank, mem, prevmem;
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// fix me later -- there are two more banks at 0x56 and 0x57
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unsigned long firstbank = 0x5a, lastbank = 0x5d;
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u8 sma_status, sma_size, sma_size_bits;
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u8 val;
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struct pci_dev *pcidev;
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pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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if (! pcidev)
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return 0;
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pci_read_config_byte(pcidev, 0xe1, &sma_status);
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sma_size_bits = (sma_status >> 4) & 0x07;
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if (sma_size_bits > 7)
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sma_size = 0;
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else
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sma_size = 0x01 << sma_size_bits;
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for(totalmem = mem = prevmem = 0, bank = firstbank;
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bank <= lastbank; bank++) {
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pci_read_config_byte(pcidev, bank, &mem);
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// sanity check. If the mem value is < prevmem,
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// that is an error, so skip this step.
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if (mem < prevmem) {
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printk_err("ERROR: bank 0x%x, mem 0x%x TOO SMALL\n",
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bank, prevmem);
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printk_err("Should be >= 0x%x\n", prevmem);
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} else
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totalmem += (mem - prevmem) * 16;
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prevmem = mem;
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}
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totalmem -= sma_size;
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totalmem *= 1024;
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#if 0
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printk_info("sizeram: returning 0x%x KB\n", totalmem);
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printk_info("sizeram: NOT returning 0x%x KB\n", totalmem);
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printk_info("sizeram: there are still some SPD problems ... \n");
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totalmem = 64 * 1024;
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printk_info("sizeram: SO we return only 0x%x KB\n", totalmem);
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#endif
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return totalmem;
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}
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struct mem_range *sizeram(void)
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{
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static struct mem_range mem[3];
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mem[0].basek = 0;
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mem[0].sizek = 640;
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mem[1].basek = 1024;
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mem[1].sizek = __sizeram();
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mem[2].basek = 0;
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mem[2].sizek = 0;
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if (mem[1].sizek == 0) {
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mem[1].sizek = 64*1024;
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}
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mem[1].sizek -= mem[1].basek;
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return mem;
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}
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#ifdef HAVE_FRAMEBUFFER
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void framebuffer_on()
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{
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unsigned long devfn;
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u16 command;
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devfn = PCI_DEVFN(0, 1);
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pcibios_read_config_word(0, devfn, 0x3e, &command);
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command |= 0x08;
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pcibios_write_config_word(0, devfn, 0x3e, command);
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}
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#endif
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/*
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* This fixup is based on capturing values from an Award bios. Without
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* this fixup the DMA write performance is awful (i.e. hdparm -t /dev/hda is
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* slower than normal, ethernet drops packets).
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* Apparently these registers govern some sort of bus master behavior.
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*/
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void northbridge_fixup(void)
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{
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struct pci_dev *pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
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if (pcidev) {
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pci_write_config_byte(pcidev, 0x70, 0xc0);
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pci_write_config_byte(pcidev, 0x71, 0x88);
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// pci_write_config_byte(pcidev, 0x72, 0xec);
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// pci_write_config_byte(pcidev, 0x73, 0x0c);
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// pci_write_config_byte(pcidev, 0x74, 0x0e);
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pci_write_config_byte(pcidev, 0x75, 0x01);
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pci_write_config_byte(pcidev, 0x76, 0x52);
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}
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}
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163
src/northbridge/via/vt8623/raminit.inc
Normal file
163
src/northbridge/via/vt8623/raminit.inc
Normal file
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@ -0,0 +1,163 @@
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/*
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* raminit.inc: Setting registers to their recommended values for vt8633
|
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*
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*
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* Copyright 2002 Cwlinux Limited
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#define loop200 $0x5000
|
||||
#define loop100 $0x2500
|
||||
|
||||
raminit:
|
||||
intel_chip_post_macro(0x35)
|
||||
|
||||
CS_WRITE($0x75, $0x08)
|
||||
|
||||
/* since we only support epia-m at the moment, only ddr is supported */
|
||||
/* setup cpu */
|
||||
CS_WRITE($0x50, $0xc8)
|
||||
CS_WRITE($0x51, $0xde)
|
||||
CS_WRITE($0x52, $0xcf)
|
||||
CS_WRITE($0x53, $0x88)
|
||||
CS_WRITE($0x55, $0x07)
|
||||
|
||||
/* DRAM MA Map Type */
|
||||
CS_WRITE($0x58, $0x71)
|
||||
|
||||
/* DRAM bank 0 - 3 size = 512M */
|
||||
CS_WRITE($0x5a, $0x08)
|
||||
CS_WRITE($0x5b, $0x08)
|
||||
CS_WRITE($0x5c, $0x08)
|
||||
CS_WRITE($0x5d, $0x08)
|
||||
|
||||
/* set DRAM Timing for all banks */
|
||||
CS_WRITE($0x64, $0xe6)
|
||||
|
||||
/* set DRAM type to DDR */
|
||||
CS_WRITE($0x60, $0x02)
|
||||
#if 0
|
||||
CS_WRITE($0x61, $0xaa)
|
||||
CS_WRITE($0x62, $0xaf)
|
||||
CS_WRITE($0x63, $0xa0)
|
||||
#endif
|
||||
/* DRAM Arbitration Timer */
|
||||
CS_WRITE($0x65, $0x32)
|
||||
CS_WRITE($0x66, $0x01)
|
||||
CS_WRITE($0x68, $0x59)
|
||||
|
||||
/* DRAM Frequency */
|
||||
CS_WRITE($0x54, $0xe0)
|
||||
CS_WRITE($0x69, $0x2d)
|
||||
|
||||
/* Enable CKE */
|
||||
CS_WRITE($0x6b, $0x10)
|
||||
|
||||
/* Disable DRAM refresh */
|
||||
CS_WRITE($0x6a, $0x00)
|
||||
|
||||
/* Set heavy drive */
|
||||
CS_WRITE($0x6d, $0x44)
|
||||
|
||||
/* NOP Command Enable */
|
||||
CS_WRITE($0x6b, $0x01)
|
||||
/* read a double word from any address of the dimm */
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop200)
|
||||
|
||||
/* All bank Precharge Command Enable */
|
||||
CS_WRITE($0x6b, $0x02)
|
||||
movl %eax, %ds:(%esi)
|
||||
|
||||
/* MSR Enable */
|
||||
CS_WRITE($0x6b, $0x03)
|
||||
/* read 0x2000h */
|
||||
movl $0x2000, %ecx
|
||||
movl (%ecx), %eax
|
||||
// movl $0x4002000, %ecx
|
||||
// movl (%ecx), %eax
|
||||
/* read 0x800h */
|
||||
movl $0x800, %ecx
|
||||
movl (%ecx), %eax
|
||||
// movl $0x4000800, %ecx
|
||||
// movl (%ecx), %eax
|
||||
|
||||
/* All banks Precharge Command Enable */
|
||||
CS_WRITE($0x6b, $0x02)
|
||||
movl %eax, %ds:(%esi)
|
||||
|
||||
/* CBR Cycle Enable */
|
||||
CS_WRITE($0x6b, $0x04)
|
||||
/* Read 8 times */
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop100)
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop100)
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop100)
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop100)
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop100)
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop100)
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop100)
|
||||
movl %eax, %ds:(%esi)
|
||||
DELAY(loop100)
|
||||
|
||||
/* MSR Enable */
|
||||
CS_WRITE($0x6b, $0x03)
|
||||
/* 0x150 if CAS Latency 2 or 0x350 CAS Latency 2.5 */
|
||||
movl $0x350, %ecx
|
||||
movl (%ecx), %eax
|
||||
// movl $0x4000350, %ecx
|
||||
// movl (%ecx), %eax
|
||||
|
||||
/* Normal SDRAM Mode */
|
||||
CS_WRITE($0x6b, $0x58)
|
||||
|
||||
/* Set the refreash rate */
|
||||
CS_WRITE($0x6a, $0x86)
|
||||
|
||||
CS_WRITE($0x67, $0x39)
|
||||
|
||||
/* pci */
|
||||
CS_WRITE($0x70, $0x82)
|
||||
CS_WRITE($0x73, $0x01)
|
||||
CS_WRITE($0x76, $0x50)
|
||||
|
||||
CS_WRITE($0x71, $0xc8)
|
||||
|
||||
#if 0
|
||||
CS_WRITE($0x80, $0x0f)
|
||||
CS_WRITE($0x84, $0x80)
|
||||
CS_WRITE($0x88, $0x02)
|
||||
|
||||
CS_WRITE($0xb8, $0x8a)
|
||||
CS_WRITE($0xe0, $0x81)
|
||||
CS_WRITE($0xe1, $0xdd)
|
||||
CS_WRITE($0xe2, $0x42)
|
||||
#endif
|
||||
/* graphics aperture base */
|
||||
CS_WRITE($0x13, $0xd0)
|
||||
|
||||
CS_WRITE($0x56, $0x10)
|
||||
CS_WRITE($0x57, $0x10)
|
||||
|
||||
intel_chip_post_macro(0x36)
|
||||
|
||||
1
src/southbridge/via/vt8235/Config
Normal file
1
src/southbridge/via/vt8235/Config
Normal file
|
|
@ -0,0 +1 @@
|
|||
object southbridge.o
|
||||
14
src/southbridge/via/vt8235/setup_ethernet.inc
Normal file
14
src/southbridge/via/vt8235/setup_ethernet.inc
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* This early setup is a handy place to enable the Ethernet if the user wants
|
||||
* it.
|
||||
*/
|
||||
enable_eth:
|
||||
movl $CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50), %eax
|
||||
PCI_READ_CONFIG_DWORD
|
||||
|
||||
/* Turn on just the Ethernet and disable modem */
|
||||
orl $0x1080, %eax
|
||||
mov %eax, %ecx
|
||||
|
||||
movl $CONFIG_ADDR(0, SUPERIO_DEVFN, 0x50), %eax
|
||||
PCI_WRITE_CONFIG_DWORD
|
||||
29
src/southbridge/via/vt8235/setup_ide.inc
Normal file
29
src/southbridge/via/vt8235/setup_ide.inc
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
config_ide:
|
||||
movl $CONFIG_ADDR(0, 0x88, 0x50), %eax
|
||||
movb $0x00, %dl
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
|
||||
movl $CONFIG_ADDR(0, 0x89, 0x04), %eax
|
||||
movb $0x07, %dl
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
|
||||
movl $CONFIG_ADDR(0, 0x89, 0x40), %eax
|
||||
movb $0x03, %dl
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
|
||||
// This early setup switches IDE into compatibility mode before PCI gets
|
||||
// a chance to assign I/Os
|
||||
#if (!ENABLE_IDE_NATIVE_MODE)
|
||||
movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
|
||||
// movb $0x09, %dl
|
||||
movb $0x00, %dl
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
|
||||
movl $CONFIG_ADDR(0, 0x89, 0x3c), %eax
|
||||
movb $0x0e, %dl
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
|
||||
movl $CONFIG_ADDR(0, 0x89, 0x3d), %eax
|
||||
movb $0x00, %dl
|
||||
PCI_WRITE_CONFIG_BYTE
|
||||
#endif
|
||||
505
src/southbridge/via/vt8235/southbridge.c
Normal file
505
src/southbridge/via/vt8235/southbridge.c
Normal file
|
|
@ -0,0 +1,505 @@
|
|||
#include <pci.h>
|
||||
#include <pc80/keyboard.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <printk.h>
|
||||
#include <pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
|
||||
// #define IDE_NATIVE_MODE 1
|
||||
|
||||
void usb_on()
|
||||
{
|
||||
unsigned char regval;
|
||||
|
||||
/* Base 8235 controller */
|
||||
struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
||||
0x3177, 0);
|
||||
/* USB controller 1 */
|
||||
struct pci_dev *dev1 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
||||
0x3038, 0);
|
||||
/* USB controller 2 */
|
||||
struct pci_dev *dev2 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
||||
0x3038, \
|
||||
dev1);
|
||||
/* USB controller 3 */
|
||||
struct pci_dev *dev3 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
||||
0x3038, \
|
||||
dev2);
|
||||
#if ENABLE_VT8235_USB
|
||||
if(dev0) {
|
||||
pci_read_config_byte(dev0, 0x50, ®val);
|
||||
regval &= ~(0x36);
|
||||
pci_write_config_byte(dev0, 0x50, regval);
|
||||
}
|
||||
|
||||
/* enable USB1 */
|
||||
if(dev1) {
|
||||
pci_write_config_byte(dev1, 0x3c, 0x05);
|
||||
pci_write_config_byte(dev1, 0x04, 0x07);
|
||||
}
|
||||
|
||||
/* enable USB2 */
|
||||
if(dev2) {
|
||||
pci_write_config_byte(dev2, 0x3c, 0x05);
|
||||
pci_write_config_byte(dev2, 0x04, 0x07);
|
||||
}
|
||||
|
||||
/* enable USB3 */
|
||||
if(dev3) {
|
||||
pci_write_config_byte(dev3, 0x3c, 0x05);
|
||||
pci_write_config_byte(dev3, 0x04, 0x07);
|
||||
}
|
||||
|
||||
#else
|
||||
if(dev0) {
|
||||
pci_read_config_byte(dev0, 0x50, ®val);
|
||||
regval |= 0x36;
|
||||
pci_write_config_byte(dev0, 0x50, regval);
|
||||
}
|
||||
|
||||
/* disable USB1 */
|
||||
if(dev1) {
|
||||
pci_write_config_byte(dev1, 0x3c, 0x00);
|
||||
pci_write_config_byte(dev1, 0x04, 0x00);
|
||||
}
|
||||
|
||||
/* disable USB2 */
|
||||
if(dev2) {
|
||||
pci_write_config_byte(dev2, 0x3c, 0x00);
|
||||
pci_write_config_byte(dev2, 0x04, 0x00);
|
||||
}
|
||||
|
||||
/* disable USB3 */
|
||||
if(dev3) {
|
||||
pci_write_config_byte(dev3, 0x3c, 0x00);
|
||||
pci_write_config_byte(dev3, 0x04, 0x00);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void keyboard_on()
|
||||
{
|
||||
unsigned char regval;
|
||||
|
||||
/* Base 8235 controller */
|
||||
struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
||||
0x3177, 0);
|
||||
|
||||
if (dev0) {
|
||||
pci_read_config_byte(dev0, 0x51, ®val);
|
||||
// regval |= 0x0f;
|
||||
/* !!!FIX let's try this */
|
||||
regval |= 0x1d;
|
||||
pci_write_config_byte(dev0, 0x51, regval);
|
||||
}
|
||||
pc_keyboard_init();
|
||||
|
||||
}
|
||||
|
||||
void nvram_on()
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Enable the ethernet device and turn off stepping (because it is integrated
|
||||
* inside the southbridge)
|
||||
*/
|
||||
void ethernet_fixup()
|
||||
{
|
||||
struct pci_dev *dev, *edev;
|
||||
u8 byte;
|
||||
|
||||
printk_info("Ethernet fixup\n");
|
||||
|
||||
edev = pci_find_device(PCI_VENDOR_ID_VIA, 0x3065, 0);
|
||||
if (edev != NULL) {
|
||||
printk_debug("Configuring VIA LAN\n");
|
||||
#if 0
|
||||
/* We don't need stepping - though the device supports it */
|
||||
pci_read_config_byte(edev, PCI_COMMAND, &byte);
|
||||
byte &= ~PCI_COMMAND_WAIT;
|
||||
pci_write_config_byte(edev, PCI_COMMAND, byte);
|
||||
|
||||
/* turn on master and pio */
|
||||
pci_read_config_byte(edev, PCI_COMMAND, &byte);
|
||||
byte = byte | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
|
||||
pci_write_config_byte(edev, PCI_COMMAND, byte);
|
||||
#endif
|
||||
} else {
|
||||
printk_debug("VIA LAN not found\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#if 1
|
||||
void southbridge_fixup()
|
||||
{
|
||||
unsigned char enables;
|
||||
struct pci_dev *dev0;
|
||||
struct pci_dev *dev1;
|
||||
struct pci_dev *devpwr;
|
||||
#if 0
|
||||
/* Base 8235 controller */
|
||||
dev0 = pci_find_device(PCI_VENDOR_ID_VIA, 0x3177, 0);
|
||||
/* IDE controller */
|
||||
dev1 = pci_find_device(PCI_VENDOR_ID_VIA, 0x0571, 0);
|
||||
|
||||
/* Map 4MB of FLASH into the address space */
|
||||
pci_write_config_byte(dev0, 0x41, 0x7f);
|
||||
|
||||
/* these follows award's values */
|
||||
pci_write_config_byte(dev0, 0x40, 0x45);
|
||||
pci_write_config_byte(dev0, 0x42, 0xf0);
|
||||
pci_write_config_byte(dev0, 0x4e, 0x0a);
|
||||
pci_write_config_byte(dev0, 0x4f, 0x08);
|
||||
pci_write_config_byte(dev0, 0x50, 0x81);
|
||||
pci_write_config_byte(dev0, 0x51, 0x1d);
|
||||
// pci_write_config_byte(dev0, 0x52, 0x09);
|
||||
pci_write_config_byte(dev0, 0x53, 0x00);
|
||||
pci_write_config_byte(dev0, 0x58, 0x20);
|
||||
pci_write_config_byte(dev0, 0x5b, 0x00);
|
||||
|
||||
/* ide */
|
||||
/* these follows award's values */
|
||||
pci_write_config_byte(dev1, 0x40, 0x03);
|
||||
pci_write_config_byte(dev1, 0x41, 0xf2);
|
||||
pci_write_config_byte(dev1, 0x42, 0x09);
|
||||
pci_write_config_byte(dev1, 0x43, 0x05);
|
||||
pci_write_config_byte(dev1, 0x44, 0x18);
|
||||
pci_write_config_byte(dev1, 0x45, 0x1c);
|
||||
pci_write_config_byte(dev1, 0x4b, 0xa8);
|
||||
pci_write_config_byte(dev1, 0x4c, 0x3f);
|
||||
pci_write_config_byte(dev1, 0x4f, 0x20);
|
||||
|
||||
pci_write_config_byte(dev1, 0x50, 0x17);
|
||||
pci_write_config_byte(dev1, 0x51, 0x17);
|
||||
pci_write_config_byte(dev1, 0x52, 0x17);
|
||||
pci_write_config_byte(dev1, 0x53, 0xe2);
|
||||
pci_write_config_byte(dev1, 0x54, 0x0c);
|
||||
pci_write_config_byte(dev1, 0x55, 0x03);
|
||||
|
||||
/* Use compatability mode - per award bios */
|
||||
pci_write_config_dword(dev1, 0x10, 0x0);
|
||||
pci_write_config_dword(dev1, 0x14, 0x0);
|
||||
pci_write_config_dword(dev1, 0x18, 0x0);
|
||||
pci_write_config_dword(dev1, 0x1c, 0x0);
|
||||
|
||||
ethernet_fixup();
|
||||
|
||||
usb_on();
|
||||
#endif
|
||||
}
|
||||
|
||||
#else
|
||||
void southbridge_fixup()
|
||||
{
|
||||
unsigned char enables;
|
||||
struct pci_dev *dev0;
|
||||
struct pci_dev *dev1;
|
||||
struct pci_dev *devpwr;
|
||||
|
||||
/* Base 8235 controller */
|
||||
dev0 = pci_find_device(PCI_VENDOR_ID_VIA, 0x3177, 0);
|
||||
/* IDE controller */
|
||||
dev1 = pci_find_device(PCI_VENDOR_ID_VIA, 0x0571, 0);
|
||||
|
||||
/* enable the internal I/O decode */
|
||||
#if 0
|
||||
enables = pci_read_config_byte(dev0, 0x6C, &enables);
|
||||
enables |= 0x80;
|
||||
pci_write_config_byte(dev0, 0x6C, enables);
|
||||
#endif
|
||||
/* follow award */
|
||||
enables = pci_read_config_byte(dev0, 0x6C, &enables);
|
||||
enables = 0x00;
|
||||
pci_write_config_byte(dev0, 0x6C, enables);
|
||||
|
||||
/* Map 4MB of FLASH into the address space */
|
||||
pci_write_config_byte(dev0, 0x41, 0x7f);
|
||||
/* let's try 0x0 to see what's happen */
|
||||
// pci_write_config_byte(dev0, 0x41, 0x00);
|
||||
|
||||
/*
|
||||
* Set bit 6 of 0x40, because Award does it (IO recovery time)
|
||||
* IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
|
||||
* interrupts can be properly marked as level triggered.
|
||||
*/
|
||||
enables = pci_read_config_byte(dev0, 0x40, &enables);
|
||||
enables |= 0x45;
|
||||
pci_write_config_byte(dev0, 0x40, enables);
|
||||
|
||||
/* Set 0x42 to 0xf0 to match Award bios */
|
||||
enables = pci_read_config_byte(dev0, 0x42, &enables);
|
||||
enables |= 0xf0;
|
||||
pci_write_config_byte(dev0, 0x42, enables);
|
||||
|
||||
/* Set bit 3 of 0x4a, to match award (dummy pci request) */
|
||||
// enables = pci_read_config_byte(dev0, 0x4a, &enables);
|
||||
// enables |= 0x08;
|
||||
// pci_write_config_byte(dev0, 0x4a, enables);
|
||||
|
||||
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
|
||||
enables = pci_read_config_byte(dev0, 0x4f, &enables);
|
||||
enables |= 0x08;
|
||||
pci_write_config_byte(dev0, 0x4f, enables);
|
||||
|
||||
/* Set 0x58 to 0x03 to match Award */
|
||||
pci_write_config_byte(dev0, 0x58, 0x03);
|
||||
#if 0
|
||||
/* enable the ethernet/RTC */
|
||||
if(dev0) {
|
||||
pci_read_config_byte(dev0, 0x51, &enables);
|
||||
enables |= 0x18;
|
||||
pci_write_config_byte(dev0, 0x51, enables);
|
||||
}
|
||||
#endif
|
||||
#ifndef DISABLE_SOUTHBRIDGE_COM_PORTS
|
||||
/* enable com1 and com2. */
|
||||
enables = pci_read_config_byte(dev0, 0x6e, &enables);
|
||||
/*
|
||||
* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 is enable
|
||||
* com port a as com1
|
||||
*/
|
||||
#if 0
|
||||
enables = 0x80 | 0x10 | 0x8 ;
|
||||
pci_write_config_byte(dev0, 0x6e, enables);
|
||||
#endif
|
||||
/* following award */
|
||||
enables = 0x00;
|
||||
pci_write_config_byte(dev0, 0x6e, enables);
|
||||
/*
|
||||
* note: this is also a redo of some port of assembly, but we want
|
||||
* everything up.
|
||||
* set com1 to 115 kbaud
|
||||
* not clear how to do this yet.
|
||||
* forget it; done in assembly.
|
||||
*/
|
||||
#endif
|
||||
|
||||
/*
|
||||
* enable IDE, since Linux won't do it.
|
||||
* First do some more things to devfn (17,0)
|
||||
* note: this should already be cleared, according to the book.
|
||||
*/
|
||||
pci_read_config_byte(dev0, 0x50, &enables);
|
||||
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
|
||||
enables &= ~8; // need manifest constant here!
|
||||
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
|
||||
pci_write_config_byte(dev0, 0x50, enables);
|
||||
|
||||
/* moved it to setupide.inc */
|
||||
#if 0
|
||||
/* set default interrupt values (IDE) */
|
||||
pci_read_config_byte(dev0, 0x4c, &enables);
|
||||
printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
|
||||
/* clear out whatever was there. */
|
||||
enables &= ~0xf;
|
||||
enables = 44;
|
||||
printk_debug("setting reg. 4c to 0x%x\n", enables);
|
||||
pci_write_config_byte(dev0, 0x4c, enables);
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
/* enable serial irq */
|
||||
pci_write_config_byte(dev0, 0x52, 0x09);
|
||||
|
||||
/* dma */
|
||||
pci_write_config_byte(dev0, 0x53, 0x00);
|
||||
|
||||
/* diskable dynamic clock stop */
|
||||
pci_write_config_byte(dev0, 0x5b, 0x00);
|
||||
|
||||
// pci_write_config_byte(dev0, 0x6c, 0x00);
|
||||
// pci_write_config_byte(dev0, 0x6e, 0x00);
|
||||
|
||||
/*
|
||||
* set up the serial port interrupts.
|
||||
* com2 to 3, com1 to 4
|
||||
*/
|
||||
// pci_write_config_byte(dev0, 0x46, 0x04);
|
||||
// pci_write_config_byte(dev0, 0x47, 0x03);
|
||||
#endif
|
||||
#if 1
|
||||
/*
|
||||
* IDE setup
|
||||
*/
|
||||
#if !(ENABLE_IDE_NATIVE_MODE)
|
||||
/*
|
||||
* Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
|
||||
* interrupts. Using PCI ints confuses linux for some reason.
|
||||
*/
|
||||
|
||||
pci_read_config_byte(dev1, 0x42, &enables);
|
||||
printk_debug("enables in reg 0x42 0x%x\n", enables);
|
||||
enables &= ~0xc0;
|
||||
pci_write_config_byte(dev1, 0x42, enables);
|
||||
pci_read_config_byte(dev1, 0x42, &enables);
|
||||
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
|
||||
#endif
|
||||
|
||||
pci_read_config_byte(dev1, 0x40, &enables);
|
||||
printk_debug("enables in reg 0x40 0x%x\n", enables);
|
||||
enables |= 3;
|
||||
pci_write_config_byte(dev1, 0x40, enables);
|
||||
pci_read_config_byte(dev1, 0x40, &enables);
|
||||
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
|
||||
|
||||
/* Enable prefetch buffers */
|
||||
pci_read_config_byte(dev1, 0x41, &enables);
|
||||
enables |= 0xf0;
|
||||
pci_write_config_byte(dev1, 0x41, enables);
|
||||
|
||||
/* Lower thresholds (cause award does it) */
|
||||
pci_read_config_byte(dev1, 0x43, &enables);
|
||||
enables &= ~0x0f;
|
||||
enables |= 0x05;
|
||||
pci_write_config_byte(dev1, 0x43, enables);
|
||||
|
||||
/* PIO read prefetch counter (cause award does it) */
|
||||
pci_write_config_byte(dev1, 0x44, 0x18);
|
||||
|
||||
/* Use memory read multiple */
|
||||
pci_write_config_byte(dev1, 0x45, 0x1c);
|
||||
|
||||
/* address decoding. */
|
||||
pci_read_config_byte(dev1, 0x9, &enables);
|
||||
printk_debug("enables in reg 0x9 0x%x\n", enables);
|
||||
/* by the book, set the low-order nibble to 0xa. */
|
||||
#if ENABLE_IDE_NATIVE_MODE
|
||||
enables &= ~0xf;
|
||||
/* cf/cg silicon needs an 'f' here. */
|
||||
enables |= 0xf;
|
||||
#else
|
||||
enables &= ~0x5;
|
||||
#endif
|
||||
|
||||
pci_write_config_byte(dev1, 0x9, enables);
|
||||
pci_read_config_byte(dev1, 0x9, &enables);
|
||||
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
|
||||
|
||||
/* standard bios sets master bit. */
|
||||
pci_read_config_byte(dev1, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 0x%x\n", enables);
|
||||
enables |= 5;
|
||||
#if 1
|
||||
/* No need for stepping - kevinh@ispiri.com */
|
||||
enables &= ~0x80;
|
||||
#endif
|
||||
pci_write_config_byte(dev1, 0x4, enables);
|
||||
pci_read_config_byte(dev1, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
|
||||
|
||||
#if (!ENABLE_IDE_NATIVE_MODE)
|
||||
/* Use compatability mode - per award bios */
|
||||
pci_write_config_dword(dev1, 0x10, 0x0);
|
||||
pci_write_config_dword(dev1, 0x14, 0x0);
|
||||
pci_write_config_dword(dev1, 0x18, 0x0);
|
||||
pci_write_config_dword(dev1, 0x1c, 0x0);
|
||||
|
||||
/* Force interrupts to use compat mode - just like Award bios */
|
||||
/* !!! FIX moved it to ide_config.inc */
|
||||
#if 0
|
||||
pci_write_config_byte(dev1, 0x3d, 0x0);
|
||||
pci_write_config_byte(dev1, 0x3c, 0xff);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
ethernet_fixup();
|
||||
|
||||
usb_on();
|
||||
|
||||
#if 0
|
||||
/* Start the rtc */
|
||||
rtc_init(0);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
pci_write_config_byte(dev1, 0x40, 0x0b);
|
||||
pci_write_config_byte(dev1, 0x41, 0xf2);
|
||||
pci_write_config_byte(dev1, 0x42, 0x09);
|
||||
pci_write_config_byte(dev1, 0x43, 0x05);
|
||||
pci_write_config_byte(dev1, 0x44, 0x18);
|
||||
pci_write_config_byte(dev1, 0x45, 0x1c);
|
||||
pci_write_config_byte(dev1, 0x4b, 0xa8);
|
||||
pci_write_config_byte(dev1, 0x4c, 0x3f);
|
||||
pci_write_config_byte(dev1, 0x4f, 0x20);
|
||||
|
||||
pci_write_config_byte(dev1, 0x50, 0x17);
|
||||
pci_write_config_byte(dev1, 0x51, 0x17);
|
||||
pci_write_config_byte(dev1, 0x52, 0x17);
|
||||
pci_write_config_byte(dev1, 0x53, 0xe2);
|
||||
pci_write_config_byte(dev1, 0x54, 0x0c);
|
||||
pci_write_config_byte(dev1, 0x55, 0x03);
|
||||
|
||||
|
||||
pci_write_config_byte(dev0, 0x6C, 0x00);
|
||||
pci_write_config_byte(dev0, 0x41, 0x7f);
|
||||
|
||||
enables = pci_read_config_byte(dev0, 0x40, &enables);
|
||||
enables |= 0x45;
|
||||
pci_write_config_byte(dev0, 0x40, enables);
|
||||
|
||||
enables = pci_read_config_byte(dev0, 0x42, &enables);
|
||||
enables |= 0xf0;
|
||||
pci_write_config_byte(dev0, 0x42, enables);
|
||||
|
||||
enables = pci_read_config_byte(dev0, 0x4f, &enables);
|
||||
enables |= 0x08;
|
||||
pci_write_config_byte(dev0, 0x4f, enables);
|
||||
|
||||
pci_write_config_byte(dev0, 0x58, 0x03);
|
||||
|
||||
enables = pci_read_config_byte(dev0, 0x6e, &enables);
|
||||
enables = 0x00;
|
||||
pci_write_config_byte(dev0, 0x6e, enables);
|
||||
|
||||
pci_read_config_byte(dev0, 0x50, &enables);
|
||||
enables &= ~8; // need manifest constant here!
|
||||
pci_write_config_byte(dev0, 0x50, enables);
|
||||
|
||||
pci_write_config_byte(dev0, 0x52, 0x09);
|
||||
pci_write_config_byte(dev0, 0x53, 0x00);
|
||||
pci_write_config_byte(dev0, 0x5b, 0x00);
|
||||
|
||||
pci_read_config_byte(dev1, 0x42, &enables);
|
||||
enables &= ~0xc0;
|
||||
pci_write_config_byte(dev1, 0x42, enables);
|
||||
|
||||
pci_read_config_byte(dev1, 0x40, &enables);
|
||||
enables |= 3;
|
||||
pci_write_config_byte(dev1, 0x40, enables);
|
||||
|
||||
pci_read_config_byte(dev1, 0x41, &enables);
|
||||
enables |= 0xf0;
|
||||
pci_write_config_byte(dev1, 0x41, enables);
|
||||
|
||||
pci_read_config_byte(dev1, 0x43, &enables);
|
||||
enables &= ~0x0f;
|
||||
enables |= 0x05;
|
||||
pci_write_config_byte(dev1, 0x43, enables);
|
||||
|
||||
pci_write_config_byte(dev1, 0x44, 0x18);
|
||||
|
||||
pci_write_config_byte(dev1, 0x45, 0x1c);
|
||||
|
||||
pci_read_config_byte(dev1, 0x9, &enables);
|
||||
enables &= ~0x5;
|
||||
pci_write_config_byte(dev1, 0x9, enables);
|
||||
|
||||
pci_read_config_byte(dev1, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 0x%x\n", enables);
|
||||
enables |= 5;
|
||||
enables &= ~0x80;
|
||||
|
||||
pci_write_config_byte(dev1, 0x4, enables);
|
||||
|
||||
pci_write_config_dword(dev1, 0x10, 0x0);
|
||||
pci_write_config_dword(dev1, 0x14, 0x0);
|
||||
pci_write_config_dword(dev1, 0x18, 0x0);
|
||||
pci_write_config_dword(dev1, 0x1c, 0x0);
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue