From 07915e145609f8097f739706a36eba21e28bdf93 Mon Sep 17 00:00:00 2001 From: Youness Alaoui Date: Tue, 7 Feb 2017 13:59:29 -0500 Subject: [PATCH] UPSTREAM: purism/librem13: Fix M.2 issues. The M.2 SSD is on the SATA port 3, which also required the DTLE setting to be set. This fixes issues with the M.2 SSD not being detected/stable. BUG=none BRANCH=none TEST=none Change-Id: I6922d284aeb07f2e32ced1cffaa47fcc1fd28637 Signed-off-by: Patrick Georgi Original-Commit-Id: a462c157f8a98e9e115e84a2d9d142c9b878210e Original-Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935 Original-Signed-off-by: Youness Alaoui Original-Reviewed-on: https://review.coreboot.org/18409 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/445827 --- src/mainboard/purism/librem13/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/purism/librem13/devicetree.cb b/src/mainboard/purism/librem13/devicetree.cb index 6bc55214d5..072e2129fb 100644 --- a/src/mainboard/purism/librem13/devicetree.cb +++ b/src/mainboard/purism/librem13/devicetree.cb @@ -24,6 +24,7 @@ chip soc/intel/broadwell # Port 0 tuning for link stability register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" device cpu_cluster 0 on device lapic 0 on end