From 06e605a5fcb9bdf13a3d301112380633b892fd4e Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 2 Sep 2016 23:48:10 -0700 Subject: [PATCH] rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ This patch fixes a typo in the clock initialization code that caused the PERILP1_PCLK_HZ constant to be ignored and the clock to always run at the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our previous tests and validation with this bug, we should probably increase the value of the constant (that had not actually been used) to the value that we had been incorrectly using instead (which also makes effective SPI read times faster). BRANCH=None BUG=chrome-os-partner:56556 TEST=Booted Kevin. Change-Id: Icb5e079f53eb22b0dbf0ea4d1c2ff08688e3fa8e Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/381031 Reviewed-by: Simon Glass --- src/soc/rockchip/rk3399/clock.c | 6 +++--- src/soc/rockchip/rk3399/include/soc/clock.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 291a70c712..c695ac0085 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -477,9 +477,9 @@ void rkclk_init(void) assert((hclk_div + 1) * PERILP1_HCLK_HZ == GPLL_HZ && (hclk_div < 0x1f)); - pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; - assert((pclk_div + 1) * PERILP1_HCLK_HZ == - PERILP1_HCLK_HZ && (hclk_div < 0x7)); + pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; + assert((pclk_div + 1) * PERILP1_PCLK_HZ == + PERILP1_HCLK_HZ && (pclk_div < 0x7)); write32(&cru_ptr->clksel_con[25], RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 9d57e46729..59260510bc 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -92,7 +92,7 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PERILP0_PCLK_HZ (49500*KHz) #define PERILP1_HCLK_HZ (99000*KHz) -#define PERILP1_PCLK_HZ (49500*KHz) +#define PERILP1_PCLK_HZ (99000*KHz) #define PWM_CLOCK_HZ PMU_PCLK_HZ