From 05aa75bd3d2744205d0b9658d2b5dede3b19f631 Mon Sep 17 00:00:00 2001
From: Bora Guvendik <bora.guvendik@intel.com>
Date: Tue, 11 Mar 2025 14:46:39 -0700
Subject: [PATCH] mb/intel/ptlrvp: Add PTL-P RVP and GCS board IDs
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This commit introduces new board ID definitions for PTL-P and GCS in the
PTLRVP mainboard code. The changes involve updating the `romstage.c` and
`memory.c` files to handle these new board IDs, ensuring that memory
configuration is correctly initialized based on the detected board
type.

Change-Id: Ia354db27a0124dcde2825e7a05a59ef5d539c4ef
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
---
 src/mainboard/intel/ptlrvp/romstage.c              | 14 +++++++++++++-
 .../baseboard/include/baseboard/variants.h         |  7 +++++++
 .../intel/ptlrvp/variants/ptlrvp/memory.c          | 14 +++++++++++++-
 3 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c
index 7b56e28e3c..b6e3681891 100644
--- a/src/mainboard/intel/ptlrvp/romstage.c
+++ b/src/mainboard/intel/ptlrvp/romstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
+#include <ec/intel/board_id.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>
 #include <string.h>
@@ -20,6 +21,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	const struct pad_config *pads;
 	size_t pads_num;
+	int board_id = get_rvp_board_id();
 	const struct mb_cfg *mem_config = variant_memory_params();
 	bool half_populated = variant_is_half_populated();
 	struct mem_spd spd_info;
@@ -32,5 +34,15 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	memset(&spd_info, 0, sizeof(spd_info));
 	variant_get_spd_info(&spd_info);
 
-	memcfg_init(memupd, mem_config, &spd_info, half_populated);
+	switch (board_id) {
+	case PTLP_LP5_T3_RVP:
+	case PTLP_LP5_T4_RVP:
+	case GCS_32GB:
+	case GCS_64GB:
+		memcfg_init(memupd, mem_config, &spd_info, half_populated);
+		break;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
 }
diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
index 2a70408e0d..5a59f1ff7c 100644
--- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
@@ -9,6 +9,13 @@
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+enum ptl_boardid {
+	PTLP_LP5_T3_RVP = 0x01,
+	PTLP_LP5_T4_RVP = 0x03,
+	GCS_32GB = 0x11,
+	GCS_64GB = 0x12,
+};
+
 /* The next set of functions return the gpio table and fill in the number of entries for
  * each table.
  */
diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
index e0908adabd..7fe2fcbe95 100644
--- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
+++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <baseboard/variants.h>
+#include <ec/intel/board_id.h>
 #include <soc/romstage.h>
 #include <soc/meminit.h>
 
@@ -66,7 +67,18 @@ static const struct mb_cfg lp5_mem_config = {
 
 const struct mb_cfg *variant_memory_params(void)
 {
-	return &lp5_mem_config;
+	int board_id = get_rvp_board_id();
+
+	switch (board_id) {
+	case PTLP_LP5_T3_RVP:
+	case PTLP_LP5_T4_RVP:
+	case GCS_32GB:
+	case GCS_64GB:
+		return &lp5_mem_config;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
 }
 
 void variant_get_spd_info(struct mem_spd *spd_info)