From 0586e0eb0fbc68a68df413b286f961aee5be845d Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 11 Mar 2025 09:57:22 -0500 Subject: [PATCH] soc/intel/alderlake: Use common ACPI code for SRAM and HECI Use the newly-created ACPI devices in common/acpi, and adjust the SoC ACPI name for the CSE/HECI device to match. Change-Id: Iabd9dec2f6838c1dc4b1cad924ceb62c992f89c0 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/86813 Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes --- src/soc/intel/alderlake/acpi/pcie.asl | 10 ---------- src/soc/intel/alderlake/acpi/southbridge.asl | 6 ++++++ src/soc/intel/alderlake/chip.c | 2 +- 3 files changed, 7 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index 50d9464169..607a861717 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -357,13 +357,3 @@ Device (PEG2) } } #endif - -Device (SRAM) -{ - Name (_ADR, 0x00140002) -} - -Device (HEC1) -{ - Name (_ADR, 0x00160000) -} diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 651d26c4ef..6de08fc13b 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -42,6 +42,12 @@ /* USB XHCI 0:14.0 */ #include "xhci.asl" +/* PMC Shared SRAM 0:14.2 */ +#include + +/* CSE/HECI #1 0:16.0 */ +#include + /* PCI _OSC */ #include diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 0256de4f82..418c6ff7be 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -153,7 +153,7 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_GBE: return "GLAN"; case PCH_DEVFN_SRAM: return "SRAM"; case PCH_DEVFN_SPI: return "FSPI"; - case PCH_DEVFN_CSE: return "HEC1"; + case PCH_DEVFN_CSE: return "HECI"; #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) case PCH_DEVFN_EMMC: return "EMMC"; #endif