Various cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@347 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann
parent
faf5bc5f1b
commit
05797ecc52
1 changed files with 116 additions and 103 deletions
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@ -1,71 +1,75 @@
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/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console.h>
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#include <io.h>
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#include <msr.h>
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#include <amd_geodelx.h>
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#include "cs5536.h"
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/*
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* cs5536_early_setup.c:Early chipset initialization for CS5536 companion device
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* This code is needed for setting up ram, since we need SMBUS working as
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* well as serial port.
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* This file implements the initialization sequence documented in section 4.2 of
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* AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
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* Early chipset initialization for the AMD CS5536 Companion Device.
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*
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* This code is needed for setting up RAM, since we need SMBus working as
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* well as a serial port.
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*
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* This file implements the initialization sequence documented in section 4.2
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* of AMD Geode GX Processor CS5536 Companion Device GoedeROM Porting Guide.
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*/
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/**
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* @brief Set up GLINK routing for this part. The routing is controlled by an MSR.
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* This appears to be the
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* same on all boards.
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* If you don't know what GLINK routing is, there is no way to explain it here.
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* Set up GLINK routing for this part.
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*
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* The routing is controlled by an MSR. This appears to be the same on
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* all boards.
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*/
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void cs5536_setup_extmsr(void)
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{
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msr_t msr;
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/* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
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/* Forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM. */
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msr.hi = msr.lo = 0x00000000;
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#if CS5536_GLINK_PORT_NUM <= 4
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#if CS5536_GLINK_PORT_NUM <= 4
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msr.lo = CS5536_DEV_NUM <<
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(unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
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(unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
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#else
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msr.hi = CS5536_DEV_NUM <<
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(unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
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(unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
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#endif
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wrmsr(GLPCI_ExtMSR, msr);
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}
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/**
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* @brief Setup PCI IDSEL for CS5536. There is a Magic Register that must be
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* Setup PCI IDSEL for CS5536. There is a Magic Register that must be
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* written so that the chip appears at the expected place in the PCI tree.
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*/
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void cs5536_setup_idsel(void)
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{
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/* write IDSEL to the write once register at address 0x0000 */
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/* Write IDSEL to the write once register at address 0x0000. */
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outl(0x1 << (CS5536_DEV_NUM + 10), 0);
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}
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/**
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* @brief Magic Bits for undocumented register.
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* You don' t need to see those papers.
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* These are not the bits you're looking for.
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* You can go about your business.
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* Magic Bits for undocumented register. You don't need to see those papers.
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* These are not the bits you're looking for. You can go about your business.
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* Move along, move along.
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*/
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void cs5536_usb_swapsif(void)
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@ -73,57 +77,61 @@ void cs5536_usb_swapsif(void)
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msr_t msr;
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msr = rdmsr(USB1_SB_GLD_MSR_CAP + 0x5);
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//USB Serial short detect bit.
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/* USB Serial short detect bit. */
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if (msr.hi & 0x10) {
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/* We need to preserve bits 32,33,35 and not clear any BIST
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* error, but clear the SERSHRT error bit */
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* error, but clear the SERSHRT error bit.
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*/
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msr.hi &= 0xFFFFFFFB;
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wrmsr(USB1_SB_GLD_MSR_CAP + 0x5, msr);
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}
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}
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/**
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* @brief Set up IO bases for SMBUS, GPIO, MFGPT, ACPI, and PM.
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* These can be changed by Linux later. We set some initial value so
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* that the resources are there as needed.
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* The values are hardcoded because, this early in the process, fancy
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* allocation can do more harm than good.
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* Set up I/O bases for SMBus, GPIO, MFGPT, ACPI, and PM.
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*
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* These can be changed by Linux later. We set some initial value so that
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* the resources are there as needed. The values are hardcoded because,
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* this early in the process, fancy allocation can do more harm than good.
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*/
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void cs5536_setup_iobase(void)
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{
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msr_t msr;
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/* setup LBAR for SMBus controller */
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/* Setup LBAR for SMBus controller. */
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msr.hi = 0x0000f001;
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msr.lo = SMBUS_IO_BASE;
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wrmsr(MDD_LBAR_SMB, msr);
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/* setup LBAR for GPIO */
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/* Setup LBAR for GPIO. */
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msr.hi = 0x0000f001;
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msr.lo = GPIO_IO_BASE;
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wrmsr(MDD_LBAR_GPIO, msr);
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/* setup LBAR for MFGPT */
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/* Setup LBAR for MFGPT. */
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msr.hi = 0x0000f001;
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msr.lo = MFGPT_IO_BASE;
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wrmsr(MDD_LBAR_MFGPT, msr);
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/* setup LBAR for ACPI */
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/* Setup LBAR for ACPI. */
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msr.hi = 0x0000f001;
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msr.lo = ACPI_IO_BASE;
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wrmsr(MDD_LBAR_ACPI, msr);
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/* setup LBAR for PM Support */
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/* Setup LBAR for PM support. */
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msr.hi = 0x0000f001;
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msr.lo = PMS_IO_BASE;
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wrmsr(MDD_LBAR_PMS, msr);
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}
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/**
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* @brief Power Button Setup
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* setup GPIO24, it is the external signal for 5536 vsb_work_aux
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* which controls all voltage rails except Vstandby & Vmem.
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* We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
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* Power Button Setup.
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*
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* Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which
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* controls all voltage rails except Vstandby & Vmem. We need to enable,
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* OUT_AUX1 and OUTPUT_ENABLE in this order.
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*
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* If GPIO24 is not enabled then soft-off will not work.
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*/
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void cs5536_setup_power_button(void)
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@ -131,39 +139,45 @@ void cs5536_setup_power_button(void)
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outl(0x40020000, PMS_IO_BASE + 0x40);
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outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
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outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
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}
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/**
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* @brief Set the various GPIOs. An unknown question at this point is
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* how general this is to all mainboards. At the same time, many
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* boards seem to follow this particular reference spec.
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* Set the various GPIOs.
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*
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* An unknown question at this point is how general this is to all mainboards.
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* At the same time, many boards seem to follow this particular reference spec.
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*/
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void cs5536_setup_smbus_gpio(void)
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{
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u32 val;
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/* setup GPIO pins 14/15 for SDA/SCL */
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/* Setup GPIO pins 14/15 for SDA/SCL. */
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val = GPIOL_15_SET | GPIOL_14_SET;
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/* Output Enable */
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outl(val, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
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/* Output AUX1 */
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outl(val, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
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/* Input Enable */
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outl(val, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
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/* Input AUX1 */
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outl(val, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
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}
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/**
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* @brief Disable the internal UART.
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* Disable the internal UART.
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*
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* Different boards have different UARTs for COM1.
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*/
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void cs5536_disable_internal_uart(void)
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{
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msr_t msr;
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/* The UARTs default to enabled.
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* Disable and reset them and configure them later. (SIO init)
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* Disable and reset them and configure them later (SIO init).
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*/
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msr = rdmsr(MDD_UART1_CONF);
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msr.lo = 1; // reset
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@ -179,15 +193,17 @@ void cs5536_disable_internal_uart(void)
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}
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/**
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* @brief Set up the cs5536 CIS interface to CPU interface to match modes.
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* The CIS is related to the interrupt system. It is important to match the
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* south and the cpu chips. At the same time, they always seem to use mode B.
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* Set up the CS5536 CIS interface to CPU interface to match modes.
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*
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* The CIS is related to the interrupt system. It is important to match
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* the southbridge and the CPU chips. At the same time, they always seem
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* to use mode B.
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*/
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void cs5536_setup_cis_mode(void)
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{
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msr_t msr;
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/* setup CPU interface serial to mode B to match CPU */
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/* Setup CPU interface serial to mode B to match CPU. */
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msr = rdmsr(GLPCI_SB_CTRL);
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msr.lo &= ~0x18;
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msr.lo |= 0x10;
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@ -195,92 +211,89 @@ void cs5536_setup_cis_mode(void)
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}
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/**
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* @brief Enable the on chip UART.see page 412 of the cs5536 companion book
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* Enable the on chip UART.
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*
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* See page 412 of the AMD Geode CS5536 Companion Device data book.
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*/
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void cs5536_setup_onchipuart(void)
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{
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msr_t msr;
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/* Setup early for polling only mode.
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* 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
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* 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1.
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* GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
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* 2. Enable UART IO space in MDD
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* 2. Enable UART I/O space in MDD.
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* MSR 0x51400014 bit 18:16
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* 3. Enable UART controller
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* 3. Enable UART controller.
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* MSR 0x5140003A bit 0, 1
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*/
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/* GPIO8 - UART1_TX */
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/* Set: Output Enable (0x4) */
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/* Set: Output Enable (0x4) */
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outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
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/* Set: OUTAUX1 Select (0x10) */
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outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
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/* GPIO9 - UART1_RX */
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/* Set: Input Enable (0x20) */
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/* Set: Input Enable (0x20) */
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outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
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/* Set: INAUX1 Select (0x34) */
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/* Set: INAUX1 Select (0x34) */
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outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
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/* set address to 3F8 */
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/* Set address to 0x3F8. */
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msr = rdmsr(MDD_LEG_IO);
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msr.lo |= 0x7 << 16;
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wrmsr(MDD_LEG_IO, msr);
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/* Bit 1 = DEVEN (device enable)
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* Bit 4 = EN_BANKS (allow access to the upper banks
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/* Bit 1 = DEVEN (device enable)
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* Bit 4 = EN_BANKS (allow access to the upper banks)
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*/
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msr.lo = (1 << 4) | (1 << 1);
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msr.hi = 0;
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/* enable COM1 */
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/* Enable COM1. */
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wrmsr(MDD_UART1_CONF, msr);
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}
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/**
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* @brief Board setup. Known to work on norwich and digitial logic boards.
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* The extmsr and cis_mode are common for sure.
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* The RSTPLL check is mandatory.
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* IDSEl of course is required, so the chip appears in PCI config space,
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* Board setup.
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*
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* Known to work on the AMD Norwich and DIGITIAL-LOGIC boards.
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*
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* The extmsr and cis_mode are common for sure. The RSTPLL check is mandatory.
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* IDSEL of course is required, so the chip appears in PCI config space,
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* and the swapsif covers a necessary chip fix.
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* Finally, the iobase is needed for DRAM, the GPIOs
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* are likely common to all boards, and the power button
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* seems to be the same on all. At the same time,
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* we may need to move gpio and power button
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* out as developments demand.
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* Note we do NOT do any UART
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* setup here -- this is done later by the mainboard setup,
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* since UART usage is not universal.
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* A comment from Marc Jones:
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"It
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would be difficult to move this to early mainboard (car_auto) because
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the IObase needs to be setup first and then SMBus setup would be
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optional etc. I think that any platform that uses the SMBus GPIOs for
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something other than SMBus will need a lot of customization anyway and
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they would have to override the generic file. I understand the desire to
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make everything generic but that really over complicates 99% of the
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designs."
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*
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* Finally, the iobase is needed for DRAM, the GPIOs are likely common to all
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* boards, and the power button seems to be the same on all. At the same time,
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* we may need to move GPIO and power button out as developments demand.
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*
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* Note we do NOT do any UART setup here -- this is done later by the
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* mainboard setup, since UART usage is not universal.
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*
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* See also a comment from Marc Jones:
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* http://www.linuxbios.org/pipermail/linuxbios/2007-June/021958.html
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*/
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void cs5536_early_setup(void)
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{
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msr_t msr;
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/* note: you can't do prints in here in most cases,
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* and we don't want to hang on serial, so they are
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* commented out
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*/
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/* Note: you can't do prints in here in most cases, and we don't want
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* to hang on serial, so they are commented out.
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*/
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cs5536_setup_extmsr();
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cs5536_setup_cis_mode();
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msr = rdmsr(GLCP_SYS_RSTPLL);
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if (msr.lo & (0x3f << 26)) {
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/* PLL is already set and we are reboot from PLL reset */
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/* PLL is already set and we are reboot from PLL reset. */
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return;
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}
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cs5536_setup_idsel();
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cs5536_usb_swapsif();
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cs5536_setup_iobase();
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cs5536_setup_smbus_gpio();
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/* cs5536_enable_smbus(); -- leave this out for now */
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/* cs5536_enable_smbus(); -- Leave this out for now. */
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cs5536_setup_power_button();
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}
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