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soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default

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Fsp configures the USB over-current pin and overrides the according pad
configuration to NF1, regardless of the port being configured as disabled.

Thus, set the OC pin to 0xff ("disabled") in this case to prevent this.

This allows us to skip setting USBx_PORT_EMPTY in the devicetree for
disabled USB ports.

Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45112
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michael Niewöhner 2020-09-04 15:40:35 +02:00 • committed by Michael Niewöhner
commit 056d552357
5 changed files with 50 additions and 30 deletions
Download patch file Download diff file Expand all files Collapse all files

21
src/soc/intel/cannonlake/fsp_params.c
View file

@ -262,15 +262,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
/* Set USB OC pin to 0 first */
for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
params->Usb2OverCurrentPin[i] = 0;
}
for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) {
params->Usb3OverCurrentPin[i] = 0;
}
mainboard_silicon_init_params(params);
const struct soc_power_limits_config *soc_config;
@ -379,12 +370,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2AfePredeemp[i] =
config->usb2_ports[i].tx_emp_enable;
params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
if (config->usb2_ports[i].enable)
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
else
params->Usb2OverCurrentPin[i] = 0xff;
}
if (config->PchUsb2PhySusPgDisable)
@ -392,7 +387,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].enable) {
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
} else {
params->Usb3OverCurrentPin[i] = 0xff;
}
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] =

20
src/soc/intel/icelake/fsp_params.c
View file

@ -64,13 +64,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Load VBT before devicetree-specific config. */
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
/* Set USB OC pin to 0 first */
for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++)
params->Usb2OverCurrentPin[i] = 0;
for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++)
params->Usb3OverCurrentPin[i] = 0;
/* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
@ -135,8 +128,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =
config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] =
config->usb2_ports[i].ocpin;
params->Usb2PhyPetxiset[i] =
config->usb2_ports[i].pre_emp_bias;
params->Usb2PhyTxiset[i] =
@ -145,11 +136,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
config->usb2_ports[i].tx_emp_enable;
params->Usb2PhyPehalfbit[i] =
config->usb2_ports[i].pre_emp_bit;
if (config->usb2_ports[i].enable)
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
else
params->Usb2OverCurrentPin[i] = 0xff;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].enable) {
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
} else {
params->Usb3OverCurrentPin[i] = 0xff;
}
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] =

14
src/soc/intel/jasperlake/fsp_params.c
View file

@ -253,19 +253,25 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* USB configuration */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
if (config->usb2_ports[i].enable)
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
else
params->Usb2OverCurrentPin[i] = 0xff;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].enable) {
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
} else {
params->Usb3OverCurrentPin[i] = 0xff;
}
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;

13
src/soc/intel/skylake/chip.c
View file

@ -139,8 +139,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] =
config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] =
config->usb2_ports[i].ocpin;
params->Usb2AfePetxiset[i] =
config->usb2_ports[i].pre_emp_bias;
params->Usb2AfeTxiset[i] =
@ -149,11 +147,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
config->usb2_ports[i].tx_emp_enable;
params->Usb2AfePehalfbit[i] =
config->usb2_ports[i].pre_emp_bit;
if (config->usb2_ports[i].enable)
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
else
params->Usb2OverCurrentPin[i] = 0xff;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].enable) {
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
} else {
params->Usb3OverCurrentPin[i] = 0xff;
}
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] =

12
src/soc/intel/tigerlake/fsp_params.c
View file

@ -148,16 +148,24 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
if (config->usb2_ports[i].enable)
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
else
params->Usb2OverCurrentPin[i] = 0xff;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
if (config->usb3_ports[i].enable) {
params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
} else {
params->Usb3OverCurrentPin[i] = 0xff;
}
if (config->usb3_ports[i].tx_de_emp) {
params->Usb3HsioTxDeEmphEnable[i] = 1;
params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;